MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 45

• Manufacturer Part Number: MC68HC908JB8JPE
• Description: IC MCU FLASH 8BIT 8K 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
† One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
Addr.
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
IRQ Status and Control
Configuration Register
USB Endpoint 0 Data
USB Endpoint 0 Data
USB Endpoint 0 Data
USB Endpoint 0 Data
USB Endpoint 0 Data
USB Endpoint 0 Data
USB Endpoint 0 Data
USB Endpoint 0 Data
Register Name
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
(CONFIG)
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
(UE0D0)
(UE0D1)
(UE0D2)
(UE0D3)
(UE0D4)
(UE0D5)
(UE0D6)
(UE0D7)
Register
(ISCR)
†
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read: UE0R07
Read: UE0R17
Read: UE0R27
Read: UE0R37
Read: UE0R47
Read: UE0R57
Read: UE0R67
Read: UE0R77
Write:
Write:
Write: UE0T07
Write: UE0T17
Write: UE0T27
Write: UE0T37
Write: UE0T47
Write: UE0T57
Write: UE0T67
Write: UE0T77
Bit 7
0
0
0
0
= Unimplemented
UE0R06
UE0R16
UE0R26
UE0R36
UE0R46
UE0R56
UE0R66
UE0R76
UE0T06
UE0T16
UE0T26
UE0T36
UE0T46
UE0T56
UE0T66
UE0T76
6
0
0
0
0
Memory Map
UE0R05
UE0R15
UE0R25
UE0R35
UE0R45
UE0R55
UE0R65
UE0R75
UE0T05
UE0T15
UE0T25
UE0T35
UE0T45
UE0T55
UE0T65
UE0T75
URSTD
5
0
0
0
UE0R04
UE0T04
UE0R14
UE0T14
UE0R24
UE0T24
UE0R34
UE0T34
UE0R44
UE0T44
UE0R54
UE0T54
UE0R64
UE0T64
UE0R74
UE0T74
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
LVID
R
4
0
0
0
= Reserved
UE0R03
UE0R13
UE0R23
UE0R33
UE0R43
UE0R53
UE0R63
UE0R73
UE0T03
UE0T13
UE0T23
UE0T33
UE0T43
UE0T53
UE0T63
UE0T73
SSREC
IRQF
3
0
0
UE0R02
UE0R12
UE0R22
UE0R32
UE0R42
UE0R52
UE0R62
UE0R72
UE0T02
UE0T12
UE0T22
UE0T32
UE0T42
UE0T52
UE0T62
UE0T72
COPRS
ACK
2
0
0
0
U = Unaffected by reset
UE0R01
UE0R11
UE0R21
UE0R31
UE0R41
UE0R51
UE0R61
UE0R71
UE0T01
UE0T11
UE0T21
UE0T31
UE0T41
UE0T51
UE0T61
UE0T71
IMASK
STOP
1
0
0
Technical Data
Monitor ROM
Memory Map
UE0R00
UE0R10
UE0R20
UE0R30
UE0R40
UE0R50
UE0R60
UE0R70
UE0T00
UE0T10
UE0T20
UE0T30
UE0T40
UE0T50
UE0T60
UE0T70
MODE
COPD
Bit 0
0
0
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