MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 95

• Manufacturer Part Number: MC68HC908JB8JPE
• Description: IC MCU FLASH 8BIT 8K 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Signal Name
OSCXCLK
OSCOUT
PORRST
PIN LOGIC
IRST
RESET
R/W
IDB
IAB
INTERNAL
PULL-UP
VDD
Clock doubler output which has twice the frequency of OSC1 from the oscillator
The OSCXCLK frequency divided by two. This signal is again divided by two in the
SIM to generate the internal bus clocks.
(Bus clock = OSCXCLK ÷ 4 = f
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Table 8-1. SIM Module Signal Name Conventions
SIM RESET STATUS REGISTER
RESET PIN CONTROL
POR CONTROL
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
Figure 8-1. SIM Block Diagram
INTERRUPT CONTROL
CLOCK
System Integration Module (SIM)
CLOCK GENERATORS
RESET
COUNTER
OSC
SIM
÷2
Description
÷ 2)
CONTROL
MASTER
RESET
LVI RESET (FROM LVI MODULE)
USB RESET (FROM USB MODULE)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
OSCXCLK (FROM CLOCK DOUBLER)
OSCOUT (FROM CLOCK DOUBLER)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
CPU INTERFACE
INTERRUPT SOURCES
System Integration Module (SIM)
Technical Data
Introduction
95