C8051F313-GM Silicon Laboratories Inc, C8051F313-GM Datasheet - Page 110

IC 8051 MCU 8K FLASH 28MLP

C8051F313-GM

Manufacturer Part Number
C8051F313-GM
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Datasheets

Specifications of C8051F313-GM

Core Size
8-Bit
Program Memory Size
8KB (8K x 8)
Oscillator Type
Internal
Core Processor
8051
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
No. Of I/o's
25
Ram Memory Size
1280Byte
Cpu Speed
25MHz
No. Of Timers
4
No. Of Pwm Channels
5
Digital Ic Case
RoHS Compliant
Rohs Compliant
Yes
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F310DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Data Rom Size
128 B
Height
0.88 mm
Length
5 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
336-1256
C8051F310/1/2/3/4/5/6/7
110
–40 to +85 °C unless otherwise specified.
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
V
Missing Clock Detector Timeout
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
V
V
V
DD
DD
DD
DD
Monitor Threshold (V
Monitor Turn-on Time
Monitor Supply Current
Ramp Time
Parameter
Table 9.1. Reset Electrical Characteristics
RST
)
I
RST = 0.0 V
Time from last system clock rising
edge to reset initiation
Delay between release of any
reset source and code execution
at location 0x0000
V
OL
DD
= 8.5 mA, V
= 0 V to V
Conditions
DD
Rev. 1.7
DD
= 2.7 V
= 2.7 to 3.6 V
0.7 x
2.40
V
Min
100
100
5.0
15
DD
2.55
Typ
220
25
20
0.3 x
Max
2.70
V
600
0.6
40
50
DD
1
Units
ms
µA
µA
µs
µs
µs
µs
V
V
V

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