MC56F8355VFGE Freescale Semiconductor, MC56F8355VFGE Datasheet - Page 21

• Manufacturer Part Number: MC56F8355VFGE
• Description: IC DSP 16BIT 60MHZ 128-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8355VFGE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 49
• Program Memory Size: 264KB (132K x 16)
• Program Memory Type: FLASH
• Ram Size: 10K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 128-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 49
• Data Ram Size: 20 KB
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Preliminary
Signal Name
(GPIOA0)
(GPIOA1)
(GPIOA2)
(GPIOA3)
(GPIOA4)
(GPIOA5)
GPIOB0
GPIOB1
GPIOB2
GPIOB3
CLKO
(A16)
(A17)
(A18)
(A19)
A10
A11
A12
A13
A8
A9
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Pin No.
15
16
17
18
19
20
27
28
29
30
6
Schmitt
Schmitt
Output
Output
Output
Output
Output
Input/
Input/
Type
disabled,
output is
output is
In reset,
disabled
pullup is
In reset,
enabled
enabled
During
56F8355 Technical Data, Rev. 17
Reset
pullup
State
Input,
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test
purposes.
See
Address Bus — A8 - A13 specify six of the address lines for
external program or data memory accesses. Depending upon the
state of the DRV bit in the EMI bus control register (BCR), A8 -
A13 and EMI control signals are tri-stated when the external bus is
inactive.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, these pins default to address bus functionality and
must be programmed as GPIO.
To deactivate the internal pullup resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
Port B GPIO — These four GPIO pins can be programmed as
input or output pins.
Address Bus — A16 - A19 specify four of the address lines for
external program or data memory accesses. Depending upon the
state of the DRV bit in the EMI bus control register (BCR), A16 -
A19 and EMI control signals are tri-stated when the external bus is
inactive.
After reset, the default state is GPIO.
To deactivate the internal pullup resistor, clear bit 0 in the
GPIOB_PUR register.
Example: GPIOB1, clear bit 1 in the GPIOB_PUR register.
Part 6.5.7
for details.
Signal Description
Signal Pins
21