MAXQ2000-RAX+ Maxim Integrated Products, MAXQ2000-RAX+ Datasheet - Page 12

• Manufacturer Part Number: MAXQ2000-RAX+
• Description: IC MCU 32K FLASH 68-QFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ2000-RAX+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 1-Wire, SPI, UART/USART
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.75 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-QFN Exposed Pad
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: JTAG, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: MAXQ
• No. Of I/o's: 50
• Ram Memory Size: 2048Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Embedded Interface Type: SPI, UART
• Rohs Compliant: Yes
• Development Tools By Supplier: MAXQ2000-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power LCD Microcontroller
12
P4.0/TCK/INT8
P4.1/TDI/INT9
P4.2/TMS
P4.3/TDO
HFXOUT
32KOUT
RESET
HFXIN
32KIN
____________________________________________________________________
GND
V
DD
HF OSC
OSC
32k
HFCLK
32KCLK
WDCLK
MAXQ2000
EMULATION/
DOWNLOAD
SCLKDIV
TCLKDIV
WATCHDOG
TIMER
DAY_AL
SYS_AL
MUXES
MUX
2:1
2:1
3
WDINT
SYSCLK
CONTROLLER
INTERRUPT
RISC CPU
16-BIT
WDDIV
T0CLK
T1CLK
T2CLK
1WINT
T0INT
T1INT
T2INT
U1INT
U2INT
IOINT
WDCLK
3WINT
HF OSC / 128
T0CLK
T1CLK
T2CLK
32KHz
RTC AND
ALARMS
3/4-WIRE (SPI)
FLASH ROM
INTERFACE
INTERFACE
MASK ROM
MULTIPLY
REGISTER
(64kByte)
DISPLAY
32k x 16
1-WIRE
TIMER0
TIMER1
TIMER2
x 8 LCD
SELECT
16 x 16
SERIAL
SERIAL
DPTR0
DPTR1
DPTR2
UART1
UART2
2k x 8
RAM
RAM
LCD
CLK
FILE
HW
OR
17
SYS_AL
DAY_AL
WKOUT_EN
RXD0
RXD1
WKUP
OWOUT
OWIN
TXD0
TXD1
SS
SCLK
MOSI
MISO
T0
T0B
T1
T2
T1B
T2B
CONTROLLER/
DRIVER
LCD
SEG[0]:SEG32
V
LCD
WK_OUT
CONTROL
LCD BIAS
VDDIO
GNDIO
Block Diagram
V
VLCD1
VLCD
VLCD2
VADJ
P5.4/SS
P5.5/MOSI
P5.6/SCLK
P5.7/MISO
P6.4/T0/WKOUT
P6.5/T0B/WKOUT
P6.1/T1/INT13
P6.0/T1B/INT12
P7.0/TX0/INT14
P7.1/RX0/INT15
P5.3/TX1/INT11
P5.2/RX1/INT10
SEG[28:31]/P3[4:7]/INT[4:7]
SEG[24:27]/P3[0:3]
SEG[16:23]/P2[0:7]
SEG[8:15]/P1[0:7]
SEG[0:3]/P0[0:3]
SEG[4:7]/P0[4:7]/INT[0:3]
GND
SEG[32]/INT16
COM[0]
COM[3:1]/SEG[33:35]
DDIO
P6.3/T2/OWIN
P6.2/T2B/OWOUT