PIC16F636-I/ST Microchip Technology, PIC16F636-I/ST Datasheet - Page 89

• Manufacturer Part Number: PIC16F636-I/ST
• Description: IC MCU FLASH 2KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F636-I/ST

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 14-TSSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, WDT
• Number Of I /o: 11
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/SPI/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Package: 14TSSOP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162057 - MPLAB ICD 2 HEADER 14DIP
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 11-1:
T
output to the first falling edge. The pulse width must fall
within T
T
demodulator output to the rising edge of the next pulse.
The pulse width must fall within T
T
edge (i.e., the sum of T
must be t
(Register 11-1), OEL<8:7> is set to ‘00’, then T
must not exceed T
T
The filter will reset, requiring a complete new successive
high and low period to enable LFDATA, under the
following conditions.
• The received high is not greater than the
• During T
• The received low is not greater than the
• The received sequence exceeds the maximum
• A Soft Reset SPI command is received.
© 2005 Microchip Technology Inc.
Note 1:
OEH
OEL
OET
INACT
configured minimum T
signal < 56 s may or may not cause a filter
Reset.
configured minimum T
T
- T
- or T
- or T
<1:0>
OEH
OET
01
01
01
01
10
10
10
10
11
11
11
11
00
is measured from the rising edge of the demodulator
is measured from rising edge to the next rising
OEH
is measured from the falling edge of the
.
OEH
value:
OEH
OEL
+ T
OEH
Typical at room temperature and
V
> T
> T
DD
t T
OEL
<1:0>
OEL
T
, a loss of signal > 56 s. A loss of
00
01
10
11
00
01
10
11
00
01
10
11
XX
OET
OET
OET
= 3.0V, 32 kHz oscillator.
OET
> T
TYPICAL OUTPUT ENABLE
FILTER TIMING
. If the Configuration Register 0
OET
OET
.
OEH
OEH
OEL
T
(ms)
and T
OEH
1
1
1
1
2
2
2
2
4
4
4
4
and T
value.
value.
Filter Disabled
OEL
OEL
OEL
T
(ms)
must not exceed
). The pulse width
OEL
1
1
2
4
1
1
2
4
1
1
2
4
t
T
OET
T
(ms)
.
OET
10
3
3
4
6
4
4
5
8
6
6
8
PIC12F635/PIC16F636/639
OEH
Preliminary
If the filter resets due to a long high (T
high-pulse timer will not begin timing again until after a
gap of T
the demodulator output.
Disabling the output enable filter disables the T
T
data. See Figure 11-10, Figure 11-11 and Figure 11-12
for examples.
When viewed from an application perspective, from the
pin input, the actual output enable filter timing must fac-
tor in the analog delays in the input path (such as
demodulator charge and discharge times).
• T
• T
The output enable filter starts immediately after T
the gap after AGC stabilization period.
11.16 Input Sensitivity Control
The AFE is designed to have typical input sensitivity of
3 mV
greater than 3 mV
AGC loop regulates the detecting signal amplitude when
the input level is greater than approximately 20 mV
This signal amplitude is called “AGC-active level”. The
AGC loop regulates the input voltage so that the input
signal amplitude range will be kept within the linear range
of the detection circuits without saturation. The AGC
Active Status bit (AGCACT<5>) in the AFE Status
Register 7 (Register 11-8) is set if the AGC loop
regulates the input voltage.
Table 11-2 shows the input sensitivity comparison when
the AGCSIG option is used. When AGCSIG option bit is
set, the demodulated output is available only when the
AGC loop is active (see Table 11-1). The AFE has also
input sensitivity reduction options per each channel. The
Configuration Register 3 (Register 11-4), Configuration
Register 4 (Register 11-5) and Configuration Register 5
(Register 11-6) have the option to reduce the channel
gains from 0 dB to approximately -30 dB.
OEL
OEH
OEL
PP
requirement and the AFE passes all received LF
. This means any input signal with amplitude
+ T
- T
E
and another low-to-high transition occurs on
DR
DR
+ T
- T
DF
DF
PP
can be detected. The AFE’s internal
DS41232B-page 87
OEH
> T
OET
OEH
), the
GAP
and
PP
,
.