Z8F0813SH005EC Zilog, Z8F0813SH005EC Datasheet - Page 14

• Manufacturer Part Number: Z8F0813SH005EC
• Description: IC Z8 ENCORE MCU FLASH 8K 20SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0813SH005EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3721

®
Z8 Encore!
Z8F0823 Series
Product Specification
xiv
Table 28. Port A–C Alternate Function Set 2 Sub-Registers (PxAFS2). . . . . . . 45
Table 29. Port A–C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 30. Port A–C Output Data Register (PxOUT). . . . . . . . . . . . . . . . . . . . . . 46
Table 31. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 32. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . 47
Table 33. LED Drive Level Low Register (LEDLVLL). . . . . . . . . . . . . . . . . . . . . 47
Table 34. Trap and Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . 49
Table 35. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 36. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 37. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 38. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 39. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . 55
Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL). . . . . . . . . . . . . . . . . . . . . 55
Table 41. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . 56
Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL). . . . . . . . . . . . . . . . . . . . . 57
Table 44. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . 57
Table 46. IRQ2 Enable Low Bit Register (IRQ2ENL). . . . . . . . . . . . . . . . . . . . . 58
Table 47. Interrupt Edge Select Register (IRQES). . . . . . . . . . . . . . . . . . . . . . . 58
Table 48. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . 59
Table 49. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 50. Timer 0–1 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 51. Timer 0–1 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 52. Timer 0–1 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . 75
Table 53. Timer 0–1 Reload Low Byte Register (TxRL). . . . . . . . . . . . . . . . . . . 75
Table 54. Timer 0–1 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . 75
Table 55. Timer 0–1 Control Register 0 (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . 76
Table 56. Timer 0–1 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . 76
Table 57. Timer 0–1 Control Register 1 (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . 77
PS025203-0405
P R E L I M I N A R Y
List of Tables