MCF53011CQT240 Freescale Semiconductor, MCF53011CQT240 Datasheet - Page 28

• Manufacturer Part Number: MCF53011CQT240
• Description: MCU 32BIT COLDFIRE EMAC 208LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF5301xr

Specifications of MCF53011CQT240

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 61
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: Cache
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Processor Series: MCF5301x
• Core: ColdFire V3
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: UART, I2C, SPI, SSI, Ethernet
• Maximum Clock Frequency: 20 MHz to 400 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 8
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M53015EVB, M53017KIT, M53017MOD
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Symbol
Preliminary Electrical Characteristics
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
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SD10
SD11
SD12
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the MCF5301x Reference Manual for more information on setting the SDRAM clock rate.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup
spec is just provided as guidance.
Frequency of operation
Clock period
Pulse width high
Pulse width low
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] output valid
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] output hold
SD_SDR_DQS output valid
SD_DQS[3:0] input setup relative to SD_CLK
SD_DQS[3:2] input hold relative to SD_CLK
Data (D[31:0]) input setup relative to SD_CLK (reference
only)
Data input hold relative to SD_CLK (reference only)
Data (D[31:0]) and data mask (SD_DQM[3:0]) output valid
Data (D[31:0]) and data mask (SD_DQM[3:0]) output hold
Characteristic
Preliminary—Subject to Change Without Notice
Table 13. SDR Timing Specifications
MCF5301x Data Sheet, Rev. 5
t
t
t
t
t
t
SDCHDMV
Symbol
SDCHACV
DQVSDCH
t
DQISDCH
t
SDCHDMI
SDCHACI
t
t
t
DVSDCH
DISDCH
DQSOV
t
SDCKH
SDCKH
SDCK
SD_CLK
SD_CLK
Does not apply. 0.5×SD_CLK fixed
0.25 ×
0.25 ×
12.5
0.45
0.45
Min
2.0
1.0
1.5
50
—
—
—
0.40 × SD_CLK
0.75 × SD_CLK
0.5 × SD_CLK
Self timed
width.
+ 1.0
+ 0.5
Max
0.55
0.55
80
20
—
—
—
—
Freescale Semiconductor
SD_CLK
SD_CLK
Unit
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
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