ATTINY20-MMHR Atmel, ATTINY20-MMHR Datasheet - Page 58

• Manufacturer Part Number: ATTINY20-MMHR
• Description: MCU AVR 2KB FLASH 12MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
58
Register Description
ATtiny20
PORTCR – Port Control Register
PUEA – Port A Pull-up Enable Control Register
PORTA – Port A Data Register
DDRA – Port A Data Direction Register
PINA – Port A Input Pins
PUEB – Port B Pull-up Enable Control Register
• Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 1 – BBMB: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port B. The interme-
diate tri-state cycle is then inserted when writing DDRBn to make an output. For further
information, see
• Bit 0 – BBMA: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port A. The interme-
diate tri-state cycle is then inserted when writing DDRAn to make an output. For further
information, see
Bit
0x08
Read/Write
Initial Value
Bit
0x03
Read/Write
Initial Value
Bit
0x02
Read/Write
Initial Value
Bit
0x01
Read/Write
Initial Value
Bit
0x00
Read/Write
Initial Value
Bit
0x07
Read/Write
Initial Value
PORTA7
PUEA7
PINA7
DDA7
R/W
R/W
R/W
R/W
N/A
R
7
–
0
R
7
0
7
0
7
0
7
7
–
0
“Break-Before-Make Switching” on page
“Break-Before-Make Switching” on page
PORTA6
PUEA6
PINA6
DDA6
R/W
R/W
R/W
R/W
N/A
R
6
R
6
–
0
6
0
6
0
6
0
6
–
0
PORTA5
PUEA5
PINA5
DDA5
R/W
R/W
R/W
R/W
N/A
5
0
5
0
5
0
5
5
–
R
0
R
5
–
0
PORTA4
PUEA4
PINA4
DDA4
R/W
R/W
R/W
R/W
N/A
4
R
4
0
4
0
4
0
4
–
0
4
–
R
0
PORTA3
PUEA3
PUEB3
PINA3
DDA3
R/W
R/W
R/W
R/W
N/A
R/W
3
0
3
0
3
3
0
3
0
R
3
–
0
46.
46.
PORTA2
PUEA2
PUEB2
PINA2
DDA2
R/W
R/W
R/W
R/W
R/W
N/A
2
2
0
2
0
2
0
2
0
R
2
–
0
PORTA1
PUEA1
PUEB1
PINA1
DDA1
R/W
BBMB
R/W
R/W
R/W
N/A
R/W
R/W
1
1
0
1
0
1
0
1
0
1
0
PORTA0
PUEA0
PUEB0
PINA0
BBMA
DDA0
R/W
R/W
R/W
N/A
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
8235B–AVR–04/11
PORTCR
PORTA
DDRA
PUEA
PUEB
PINA