ATTINY20-MMHR Atmel, ATTINY20-MMHR Datasheet - Page 80

• Manufacturer Part Number: ATTINY20-MMHR
• Description: MCU AVR 2KB FLASH 12MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3
12.4
80
Timer/Counter Clock Sources
Counter Unit
ATtiny20
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS1[2:0]) bits
located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and
prescaler, see
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 12-2
Figure 12-2. Counter Unit Block Diagram
Description of internal signals used in
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNT1H value when the TCNT1L is read, and
TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS1[2:0]). When no clock source is selected (CS1[2:0] = 0)
the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clk
count operations.
Count
Direction
Clear
clk
TOP
BOTTOM
TCNTnH (8-bit)
TEMP (8-bit)
T1
TCNTn (16-bit Counter)
T1
shows a block diagram of the counter and its surroundings.
DATA BUS
is present or not. A CPU write overrides (has priority over) all counter clear or
“Timer/Counter Prescaler” on page
TCNTnL (8-bit)
T1
(8-bit)
). The clk
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter1 clock.
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
T1
can be generated from an external or internal clock source,
Figure
Direction
Count
Clear
12-2:
Control Logic
TOP
105.
BOTTOM
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
8235B–AVR–04/11
Tn