PIC16F88-E/P Microchip Technology, PIC16F88-E/P Datasheet - Page 104

• Manufacturer Part Number: PIC16F88-E/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-E/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F87/88
11.2
In this mode, the AUSART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip, dedicated, 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The AUSART transmits
and receives the LSb first. The transmitter and receiver
are functionally independent, but use the same data
format and baud rate. The Baud Rate Generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit).
Asynchronous mode is stopped during Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The AUSART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
11.2.1
The AUSART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one T
empty and flag bit, TXIF (PIR1<4>), is set. This
FIGURE 11-1:
DS30487C-page 102
AUSART Asynchronous Mode
TXIE
AUSART ASYNCHRONOUS
TRANSMITTER
Interrupt
TXIF
TXEN
Baud Rate Generator
AUSART TRANSMIT BLOCK DIAGRAM
CY
SPBRG
), the TXREG register is
Baud Rate CLK
MSb
(8)
TX9D
TXREG Register
TSR Register
TX9
8
Data Bus
interrupt can be enabled/disabled by setting/clearing
enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set,
regardless of the state of enable bit TXIE and cannot be
cleared in software. It will reset only when new data is
loaded into the TXREG register. While flag bit TXIF
indicates the status of the TXREG register, another bit,
TRMT (TXSTA<1>), shows the status of the TSR
register. Status bit TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit, so the user has to poll this bit in order to
determine if the TSR register is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 11-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 11-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RB5/SS/TX/CK pin will
revert to high-impedance.
In order to select 9-bit transmission, transmit bit, TX9
(TXSTA<6>), should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG
register can result in an immediate transfer of the data
to the TSR register (if the TSR is empty). In such a
case, an incorrect ninth data bit may be loaded in the
TSR register.
Note 1: The TSR register is not mapped in data
LSb
0
TRMT
2: Flag bit TXIF is set when enable bit TXEN
memory, so it is not available to the user.
is set. TXIF is cleared by loading TXREG.
and Control
Pin Buffer
SPEN
 2005 Microchip Technology Inc.
RB5/SS/TX/CK pin