PIC16F88-E/P Microchip Technology, PIC16F88-E/P Datasheet - Page 136

• Manufacturer Part Number: PIC16F88-E/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-E/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F87/88
15.8
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR occurs.
Then, OST starts counting 1024 oscillator cycles when
PWRT ends (LP, XT, HS). When the OST ends, the
device comes out of Reset.
If MCLR is kept low long enough, all delays will expire.
Bringing MCLR high will begin execution immediately.
This is useful for testing purposes, or to synchronize
more than one PIC16F87/88 device operating in
parallel.
Table 15-3 shows the Reset conditions for the
STATUS, PCON and PC registers, while Table 15-4
shows the Reset conditions for all the registers.
TABLE 15-1:
TABLE 15-2:
DS30487C-page 134
XT, HS, LP
EXTRC, INTRC
T1OSC
Note 1:
Legend: u = unchanged, x = unknown
Configuration
Oscillator
POR
0
0
0
1
1
1
1
1
Time-out Sequence
CPU start-up is always invoked on POR, BOR and wake-up from Sleep. The 5-10 s delay is based on a
1 MHz system clock.
BOR
x
x
x
0
1
1
1
1
TIME-OUT IN VARIOUS SITUATIONS
STATUS BITS AND THEIR SIGNIFICANCE
T
PWRT
PWRTE = 0
+ 1024 • T
T
PWRT
—
TO
1
0
x
1
0
0
u
1
Power-up
OSC
PD
1
x
0
1
1
0
u
0
PWRTE = 1
1024 • T
5-10 s
—
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during Normal Operation
MCLR Reset during Sleep or Interrupt Wake-up from Sleep
OSC
(1)
T
PWRT
15.9
The Power Control/Status Register, PCON, has two
bits to indicate the type of Reset that last occurred.
Bit 0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent Resets to see if
bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable.
Bit 1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
PWRTE = 0
+ 1024 • T
T
PWRT
—
Brown-out Reset
Power Control/Status Register
(PCON)
OSC
PWRTE = 1
1024 • T
5-10 s
 2005 Microchip Technology Inc.
—
OSC
(1)
Wake-up from
1024 • T
5-10 s
5-10 s
Sleep
OSC
(1)
(1)