PIC16F88-E/P Microchip Technology, PIC16F88-E/P Datasheet - Page 108

• Manufacturer Part Number: PIC16F88-E/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-E/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F87/88
11.2.3
When setting up an asynchronous reception with
address detect enabled:
• Initialize the SPBRG register for the appropriate
• Enable the asynchronous serial port by clearing
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 11-6:
DS30487C-page 106
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
bit SYNC and setting bit SPEN.
RB2/SDO/RX/DT
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
F
OSC
AUSART RECEIVE BLOCK DIAGRAM
Baud Rate Generator
x64 Baud Rate CLK
SPBRG
and Control
Pin Buffer
SPEN
RSR<8>
ADDEN
ADDEN
RX9
RX9
Recovery
Interrupt
Data
or
64
16
CREN
Enable
Load of
Receive
Buffer
• Flag bit RCIF will be set when reception is
• Read the RCSTA register to get the ninth bit and
• Read the 8-bit received data by reading the
• If any error occurred, clear the error by clearing
• If the device has been addressed, clear the
complete and an interrupt will be generated if
enable bit RCIE was set.
determine if any error occurred during reception.
RCREG register to determine if the device is
being addressed.
enable bit CREN.
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer and interrupt the
CPU.
RCIF
RCIE
RX9
Stop
MSb
RX9D
(8)
OERR
7
RSR Register
RCREG Register
 2005 Microchip Technology Inc.
8
Data Bus
8
8
1
FERR
0
Start
LSb
FIFO