PIC16F88-E/P Microchip Technology, PIC16F88-E/P Datasheet - Page 96

• Manufacturer Part Number: PIC16F88-E/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-E/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F87/88
An SSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF, must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit, SSPIF, is set on the falling edge of
the ninth clock pulse.
As a slave transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
TABLE 10-2:
FIGURE 10-6:
FIGURE 10-7:
DS30487C-page 94
Note 1:
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Transfer is Received
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
Status Bits as Data
BF
0
1
1
0
S
S
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
A7 A6 A5 A4 A3 A2 A1
1
SSPOV
2
A7
Receiving Address
1
Data is
sampled
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
3
A6
2
I
4
I
2
2
C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
A5
Receiving Address
3
5
SSPSR
A4
6
4
R/W = 0
7
A3
5
8
Yes
No
No
No
A2
6
ACK
9
SSPBUF
A1
7
D7
1
D6
2
R/W = 1
8
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
9
ACK
Generate ACK Pulse
D4
Bit SSPOV is set because the SSPBUF register is still full
responds to SSPIF
4
SCL held low
while CPU
D3
5
D2
6
Yes
the data transfer is complete. When the ACK is latched
by the slave device, the slave logic is reset (resets
SSPSTAT register) and the slave device then monitors
for another occurrence of the Start bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register which also loads the SSPSR
register. Then, pin RB4/SCK/SCL should be enabled
by setting bit CKP.
No
No
No
D1
7
D7
SSPBUF is written in software
D0
8
1
ACK
9
D6
2
Cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
D7
1
D5
3
D6
2
(SSP Interrupt Occurs if Enabled)
D4
4
D5
Receiving Data
3
D4
Transmitting Data
D3
4
5
 2005 Microchip Technology Inc.
ACK is not sent
D3
5
D2
6
Set SSPIF Bit
D2
6
From SSP Interrupt
Service Routine
D1
7
Yes
Yes
Yes
Yes
D1
7
D0
D0
8
8
ACK
9
ACK
9
Bus master
terminates
transfer
P
P