ATMEGA3250PV-10AUR Atmel, ATMEGA3250PV-10AUR Datasheet - Page 166

• Manufacturer Part Number: ATMEGA3250PV-10AUR
• Description: MCU AVR 32K FLASH 10MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250PV-10AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.1
166
ATmega325P/3250P
Internal Clock Generation – The Baud Rate Generator
operation.
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCK bits.
Table 18-3
ing the UBRRn value for each mode of operation using an internally generated clock source.
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or when
xcki
xcko
fosc
contains equations for calculating the baud rate (in bits per second) and for calculat-
Input from XCK pin (internal Signal). Used for synchronous slave
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
Figure 18-2 on page
osc
/(UBRRn+1)). The Transmitter divides the
165.
8023F–AVR–07/09