ATMEGA3250PV-10AUR Atmel, ATMEGA3250PV-10AUR Datasheet - Page 239

• Manufacturer Part Number: ATMEGA3250PV-10AUR
• Description: MCU AVR 32K FLASH 10MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250PV-10AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 23-4.
Note:
8023F–AVR–07/09
Signal
Name
NEGSEL_2
NEGSEL_1
NEGSEL_0
PASSEN
PRECH
SCTEST
ST
VCCREN
1. Incorrect setting of the switches in
choices to the S&H circuitry on the negative input of the output comparator in
selected from either one ADC pin, Bandgap reference source, or Ground.
Boundary-scan Signals for the ADC
Direction as
seen
from the ADC
Input
Input
Input
Input
Input
Input
Input
Input
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the differential amplifier during scan. Switch-Cap
based differential amplifier require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential amplifier is therefore
not provided.
The AVR ADC is based on the analog circuitry shown in
mation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
• The port pin for the ADC channel in use must be configured to be an input with pull-up disabled
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
to avoid signal contention.
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
Description
Input Mux for negative input for differential
signal, bit 2
Input Mux for negative input for differential
signal, bit 1
Input Mux for negative input for differential
signal, bit 0
Enable pass-gate of differential amplifier.
Precharge output latch of comparator.
(Active low)
Switch-cap TEST enable. Output from
differential amplifier send out to Port Pin
having ADC_4
Output of differential amplifier will settle
faster if this signal is high first two ACLK
periods after AMPEN goes high.
Selects Vcc as the ACC reference voltage.
Figure 23-8
(1)
will make signal contention and may damage the part. There are several input
(Continued)
Recommende
d Input when
not in use
0
0
0
1
0
0
0
1
Figure
Figure 23-8
ATmega325P/3250P
23-8. Make sure only one path is
Output Values when
recommended inputs are
used, and CPU is not using the
ADC
with a successive approxi-
Table 23-4
0
0
0
1
1
0
0
0
should
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