PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 261

IC PIC MCU 128KB FLASH 28QFN

PIC18LF27J53-I/ML

Manufacturer Part Number
PIC18LF27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF27J53-I/ML
Manufacturer:
ATMEL
Quantity:
101
REGISTER 15-6:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
Master mode:
bit 7-0
10-Bit Slave mode — Most Significant Address byte:
bit 7-3
bit 2-1
bit 0
10-Bit Slave mode — Least Significant Address byte:
bit 7-0
7-Bit Slave mode:
bit 7-1
bit 0
R/W-0
ADD<7:0>: Baud Rate Clock Divider bits
SCLx pin clock period = ((ADD<7:0> + 1) *4)/F
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I
are compared by hardware and are not affected by the value in this register.
ADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
ADD<7:0>: Eight Least Significant bits of 10-bit address
ADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
R/W-0
SSPXADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0
R/W-0
2
Preliminary
C specification and must be equal to ‘11110’. However, those bits
ADD<7:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
OSC
R/W-0
PIC18(L)F2X/4XK22
R/W-0
R/W-0
2
C MODE)
DS41412D-page 261
R/W-0
bit 0

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