AT90CAN64-16AUR Atmel, AT90CAN64-16AUR Datasheet - Page 313

• Manufacturer Part Number: AT90CAN64-16AUR
• Description: MCU AVR 64K FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7679H–CAN–08/08
Table 23-7.
Note:
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
Cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
The AVR ADC is based on the analog circuitry shown in
imation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
Signal
Name
SCTEST
ST
VCCREN
• The port pin for the ADC channel in use must be configured to be an input with pull-up
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
disabled to avoid signal contention.
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
low (Sample mode).
1. Incorrect setting of the switches in
the part. There are several input choices to the S&H circuitry on the negative input of the out-
put comparator in
Bandgap reference source, or Ground.
Boundary-scan Signals for the ADC
Direction
as Seen
from the
ADC
Input
Input
Input
The upper limit is: [ 1024 * 1.5V * 1.05 / 5V ] = 323 = 0x143
The lower limit is: [ 1024 * 1.5V * 0.95 / 5V ] = 291 = 0x123
Description
Switch-cap TEST
enable. Output from x10
gain stage send out to
Port Pin having ADC_4
Output of gain stages will
settle faster if this signal
is high first two ACLK
periods after AMPEN
goes high.
Selects Vcc as the ACC
reference voltage.
Figure
23-10. Make sure only one path is selected from either one ADC pin,
Figure 23-10
(1)
Recommended
Input
when not in use
(Continued)
will make signal contention and may damage
Figure 23-10
AT90CAN32/64/128
0
0
0
CC.
with a successive approx-
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
Table 23-7
0
0
0
should
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