PIC18LF47J53-I/ML Microchip Technology, PIC18LF47J53-I/ML Datasheet - Page 267

• Manufacturer Part Number: PIC18LF47J53-I/ML
• Description: IC PIC MCU 128KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF47J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 16-4:
TABLE 16-1:
 2010 Microchip Technology Inc.
BAUDCON1
BAUDCON2
INTCON
IPR1
IPR3
PIE1
PIE3
PIR1
PIR3
PMD0
RCSTA1
RCSTA2
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TXREG1
TXSTA1
TXREG2
TXSTA2
Legend:
(Interrupt Reg. Flag)
Note:
Reg. Empty Flag)
Write to TXREGx
Name
(Transmit Shift
TXx/CKx
BRG Output
(Shift Clock)
TRMT bit
TXxIF bit
— = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.
This timing diagram shows two consecutive transmissions.
pin
UART2MD UART1MD TMR6MD
GIE/GIEH
ABDOVF
ABDOVF
SSP2IP
SSP2IE
SSP2IF
CSRC
CSRC
SPEN
SPEN
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
—
—
—
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
1 T
CY
Transmit Shift Reg
Word 1
Word 1
PEIE/GIEL
BCL2IP
BCL2IE
BCL2IF
RCIDL
RCIDL
ADIP
ADIE
Bit 6
ADIF
RX9
RX9
TX9
TX9
Start bit
Word 2
TMR0IE
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, High Byte
DTRXP
DTRXP
EUSART1 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, Low Byte
RC1IP
RC2IP
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TXEN
TXEN
Bit 5
1 T
CY
EUSART1 Transmit Register
EUSART2 Transmit Register
bit 0
Preliminary
TMR5MD
CKTXP
CKTXP
INT0IE
TX1IP
TX2IP
TX1IE
TX2IE
TX1IF
TX2IF
CREN
CREN
SYNC
SYNC
Bit 4
bit 1
Word 1
TMR4MD
CTMUIP
CTMUIE
CTMUIF
SSP1IP
SSP1IE
ADDEN
ADDEN
SSP1IF
SENDB
SENDB
BRG16
BRG16
RBIE
Bit 3
PIC18(L)F2X/4XK22
TMR3MD
TMR5GIP TMR3GIP TMR1GIP
TMR5GIE TMR3GIE TMR1GIE
TMR5GIF
TMR0IF
CCP1IP
CCP1IE
CCP1IF
BRGH
BRGH
FERR
FERR
Bit 2
—
—
bit 7/8
TMR2MD
TMR3GIF TMR1GIF
Word 2
Transmit Shift Reg
TMR2IP
TMR2IE
TMR2IF
Stop bit
INT0IF
OERR
OERR
TRMT
TRMT
WUE
WUE
Bit 1
Start bit
TMR1MD
TMR1IP
TMR1IE
TMR1IF
DS41412D-page 267
ABDEN
ABDEN
RX9D
RX9D
TX9D
TX9D
Bit 0
RBIF
Word 2
Values
bit 0
Reset
Page
274
274
115
127
129
123
125
118
120
273
273
272
272
on
56
—
—
—
—
—
—