AT89C51RE2-RLTUM Atmel, AT89C51RE2-RLTUM Datasheet - Page 22

• Manufacturer Part Number: AT89C51RE2-RLTUM
• Description: MCU 8051 128K FLASH 44-VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Height: 1.45 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10.1 mm
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Expanded RAM
(XRAM)
Figure 6. Internal and External Data Memory Address
22
AT89C51RE2
0FFh to 1FFFh
00
The AT89C51RE2 provides additional Bytes of random access memory (RAM) space for
increased data parameter handling and high level language usage.
AT89C51RE2 devices have expanded RAM in external data space configurable up to 8192bytes
(see Table 18.).
The AT89C51RE2 has internal data memory that is mapped into four separate segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128
bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same
address space as the SFR. That means they have the same address, but are physically sepa-
rate from SFR space.
When an instruction accesses an internal location above address 7Fh, the CPU knows whether
the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used
in the instruction.
•
•
•
addressable.
only.
EXTRAM bit cleared in the AUXR register (see Table 18).
Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,
accesses the SFR at location 0A0h (which is P2).
Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For
example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address
0A0h, rather than P2 (whose address is 0A0h).
The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and
MOVX instructions. This part of memory which is physically located on-chip, logically
occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide
a part of the available XRAM as explained in Table 18. This can be useful if external
peripherals are mapped at addresses already used by the internal XRAM.
XRAM
0FFh
80h
7Fh
00
indirect accesses
direct or indirect
128 bytes
128 bytes
accesses
Internal
Internal
Upper
Lower
Ram
Ram
0FFh
80h
direct accesses
Function
Register
Special
00FFh up to 1FFFh
0FFFFh
0000
External
Memory
Data
7663E–8051–10/08