ATMEGA1280V-8AUR Atmel, ATMEGA1280V-8AUR Datasheet - Page 374

• Manufacturer Part Number: ATMEGA1280V-8AUR
• Description: MCU AVR 128K FLASH 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1280V-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.7
2549M–AVR–09/10
5. This requirement applies to all ATmega640/1280/1281/2560/2561 2-wire Serial Interface operation. Other devices con-
6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/f
SPI Timing Characteristics
nected to the 2-wire Serial Bus need only obey the general f
must be greater than 6 MHz for the low time requirement to be strictly met at f
low time requirement will not be strictly met for f
devices connected to the bus may communicate at full speed (400 kHz) with other ATmega640/1280/1281/2560/2561
devices, as well as any other device with a proper t
Figure 30-6. 2-wire Serial Bus Timing
See
Table 30-6.
Note:
SCL
SDA
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 30-7 on page 375
t
SU;STA
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
- 3 t
SS high to tri-state
SCK to out high
SCK high/low
SCK to SS high
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
SPI Timing Parameters
Description
CLCL
CLCL
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
Setup
Setup
Hold
Hold
for f
for f
CK
CK
t
HD;STA
< 12 MHz
> 12 MHz
(1)
t
SCL
of
t
LOW
and
LOW
> 308 kHz when f
ATmega640/1280/1281/2560/2561
acceptance margin.
Figure 30-8 on page 375
Master
Master
Master
Master
Master
Master
Master
Master
Mode
t
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
HIGH
SCL
t
HD;DAT
requirement.
CK
t
LOW
4 • t
2 • t
= 8 MHz. Still, ATmega640/1280/1281/2560/2561
Min
10
t
20
20
ck
ck
ck
SCL
t
SU;DAT
= 100 kHz.
for details.
See
50% duty cycle
page 203
Table 20-5 on
0.5 • t
Typ
3.6
10
10
10
10
15
15
10
sck
t
SCL
SCL
SU;STO
- 2/f
- 2/f
t
r
1600
Max
CK
CK
), thus the
), thus f
t
BUF
ns
374
CK