PIC17LC756A-08I/PT Microchip Technology, PIC17LC756A-08I/PT Datasheet - Page 200

• Manufacturer Part Number: PIC17LC756A-08I/PT
• Description: IC MCU OTP 16KX16 A/D 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC17
• No. Of I/o's: 50
• Ram Memory Size: 902Byte
• Cpu Speed: 33MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC17LC756A-08IPT

PIC17C7XX
TABLE 18-2:
DS30289B-page 200
Mnemonic,
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC f,d
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DAW
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVFP
MOVPF
MOVWF
MULWF
NEGW
NOP
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBWF
SUBWFB f,d
SWAPF
TABLRD
TABLWT
TLRD
TLWT
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into the LSB of the
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte), in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead a NOP is executed.
(WREG) is required to be affected, then f = WREG must be specified.
PC (PCL).
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
f,d
f,d
f,s
f,d
f
f
f
f,s
f,d
f,d
f,d
f,d
f,d
f,d
f,d
f,p
p,f
f
f
f,s
—
f,d
f,d
f,d
f,d
f,s
f,d
f,d
t,i,f
t,i,f
t,f
t,f
PIC17CXXX INSTRUCTION SET
Description
ADD WREG to f
ADD WREG and Carry bit to f
AND WREG with f
Clear f, or Clear f and Clear WREG
Complement f
Compare f with WREG, skip if f = WREG
Compare f with WREG, skip if f > WREG
Compare f with WREG, skip if f < WREG
Decimal Adjust WREG Register
Decrement f
Decrement f, skip if 0
Decrement f, skip if not 0
Increment f
Increment f, skip if 0
Increment f, skip if not 0
Inclusive OR WREG with f
Move f to p
Move p to f
Move WREG to f
Multiply WREG with f
Negate WREG
No Operation
Rotate left f through Carry
Rotate left f (no carry)
Rotate right f through Carry
Rotate right f (no carry)
Set f
Subtract WREG from f
Subtract WREG from f with Borrow
Swap f
Table Read
Table Write
Table Latch Read
Table Latch Write
Cycles
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2 (3)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
0000
0001
0000
0010
0001
0011
0011
0011
0010
0000
0001
0010
0001
0001
0010
0000
011p
010p
0000
0011
0010
0000
0001
0010
0001
0010
0010
0000
0000
0001
1010
1010
1010
1010
MSb
16-bit Opcode
111d ffff ffff
000d ffff ffff
101d ffff ffff
100s ffff ffff
001d ffff ffff
0001 ffff ffff
0010 ffff ffff
0000 ffff ffff
111s ffff ffff
011d ffff ffff
011d ffff ffff
011d ffff ffff
010d ffff ffff
111d ffff ffff
010d ffff ffff
100d ffff ffff
pppp ffff ffff
pppp ffff ffff
0001 ffff ffff
0100 ffff ffff
110s ffff ffff
0000 0000 0000
101d ffff ffff
001d ffff ffff
100d ffff ffff
000d ffff ffff
101s ffff ffff
010d ffff ffff
001d ffff ffff
110d ffff ffff
10ti ffff ffff
11ti ffff ffff
00tx ffff ffff
01tx ffff ffff
2000 Microchip Technology Inc.
LSb
Status
Affected
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
C
Z
Z
Z
Z
None
Notes
2,6,8
2,6,8
6,8
6,8
6,8
6,8
6,8
1,3
3
3
3
1
1
7
5