PIC17LC756A-08I/PT Microchip Technology, PIC17LC756A-08I/PT Datasheet - Page 287

• Manufacturer Part Number: PIC17LC756A-08I/PT
• Description: IC MCU OTP 16KX16 A/D 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC17
• No. Of I/o's: 50
• Ram Memory Size: 902Byte
• Cpu Speed: 33MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC17LC756A-08IPT

APPENDIX A:
The following is the list of modifications over the
PIC16CXX microcontroller family:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Multiple Interrupt vectors added. This can
11. Stack size is increased to 16 deep.
12. BSR register for data memory paging.
13. Wake-up from SLEEP operates slightly differently.
14. The Oscillator Start-Up Timer (OST) and Power-
15. PORTB interrupt-on-change feature works on
16. TMR0 is 16-bit, plus 8-bit prescaler.
17. Second indirect addressing register added
18. Hardware multiplier added (8 x 8
19. Peripheral modules operate slightly differently.
20. A/D has both V
21. USARTs do not implement BRGH feature.
22. Oscillator modes slightly redefined.
23. Control/Status bits and registers have been
24. In-circuit serial programming is implemented
2000 Microchip Technology Inc.
Instruction word length is increased to 16-bit.
This allows larger page sizes, both in program
memory (8 Kwords verses 2 Kwords) and regis-
ter file (256 bytes versus 128 bytes).
Four modes of operation: Microcontroller,
Protected Microcontroller, Extended Micro-
controller, and Microprocessor.
22 new instructions.
The MOVF, TRIS and OPTION instructions are
no longer supported.
Four new instructions (TLRD, TLWT, TABLRD,
TABLWT) for transferring data between data
memory and program memory. They can be used
to “self program” the EPROM program memory.
Single cycle data memory to data memory trans-
fers possible (MOVPF and MOVFP instructions).
These instructions do not affect the Working
register (WREG).
W register (WREG) is now directly addressable.
A PC high latch register (PCLATH) is extended
to 8-bits. The PCLATCH register is now both
readable and writable.
Data memory paging is redefined slightly.
DDR registers replace function of TRIS regis-
ters.
decrease the latency for servicing interrupts.
Up Timer (PWRT) operate in parallel and not in
series.
all eight port pins.
(FSR1 and FSR2). Control bits can select the
FSR registers to auto-increment, auto-decre-
ment, remain unchanged after an indirect
address.
placed in different registers and the control bit
for globally enabling interrupts has inverse
polarity.
differently.
REF
MODIFICATIONS
+ and V
REF
- inputs.
16-bit).
APPENDIX B:
To
PIC17CXXX, the user should take the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. WDT time-outs always reset the device (in run
B.1
To convert code from the PIC17C42 to all the other
PIC17CXXX devices, the user should take the follow-
ing steps.
1.
2.
3.
Note:
Remove any TRIS and OPTION instructions,
and implement the equivalent code.
Separate the Interrupt Service Routine into its
four vectors.
Replace:
MOVF
with:
MOVFP
Replace:
MOVF
MOVWF
with:
MOVPF
or
MOVFP
Ensure that all bit names and register names are
updated to new data memory map locations.
Verify data memory banking.
Verify mode of operation for indirect addressing.
Verify peripheral routines for compatibility.
Weak pull-ups are enabled on RESET.
or SLEEP mode).
If the hardware multiply is to be used, ensure
that any variables at address 18h and 19h are
moved to another address.
Ensure that the upper nibble of the BSR was not
written with a non-zero value. This may cause
unexpected operation since the RAM bank is no
longer 0.
The disabling of global interrupts has been
enhanced, so there is no additional testing of the
GLINTD bit after a BSF
instruction.
convert
Upgrading from PIC17C42 Devices
If REG1 and REG2 are both at addresses
greater then 20h, two instructions are
required.
MOVFP
MOVPF
REG1, REG2 ; Addr(REG2)<20h
code
REG1, W
REG1, WREG
REG1, W
REG2
REG1, REG2 ; Addr(REG1)<20h
REG1, WREG ;
WREG, REG2 ;
COMPATIBILITY
written
PIC17C7XX
for
CPUSTA,
DS30289B-page 287
PIC16CXXX
GLINTD
to