PIC17LC756A-08I/PT Microchip Technology, PIC17LC756A-08I/PT Datasheet - Page 86

• Manufacturer Part Number: PIC17LC756A-08I/PT
• Description: IC MCU OTP 16KX16 A/D 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC17
• No. Of I/o's: 50
• Ram Memory Size: 902Byte
• Cpu Speed: 33MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC17LC756A-08IPT

PIC17C7XX
10.7
PORTG is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is DDRG. A ’1’ in
DDRG configures the corresponding port pin as an
input. A ’0’ in the DDRG register configures the corre-
sponding port pin as an output. Reading PORTG reads
the status of the pins, whereas writing to PORTG will
write to the port latch.
The lower four bits of PORTG are multiplexed with four
channels of the 10-bit A/D converter.
The remaining bits of PORTG are multiplexed with
peripheral output and inputs. RG4 is multiplexed with
the CAP3 input, RG5 is multiplexed with the PWM3
output, RG6 and RG7 are multiplexed with the
USART2 functions.
Upon RESET, RG3:RG0 is automatically configured as
analog inputs and must be configured in software to be
a digital I/O.
FIGURE 10-14:
DS30289B-page 86
WR PORTG
WR DDRG
RD PORTG
Note: I/O pins have protection diodes to V
V
Data Bus
AIN
PORTG and DDRG Registers
PCFG3:PCFG0
CHS3:CHS0
BLOCK DIAGRAM OF RG3:RG0
Data Latch
DDRG Latch
D
CK
D
CK
RD DDRG
Q
Q
Q
Q
DD
and V
SS
Q
.
EN
EN
D
Example 10-7 shows the instruction sequence to initial-
ize PORTG. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
EXAMPLE 10-7:
To other pads
To other pads
CLRF
MOVWF
MOVLB
MOVLW
MOVPF
MOVLW
PORTG, F
5
0x0E
WREG, ADCON1
DDRG
0x03
V
V
P
N
DD
SS
INITIALIZING PORTG
2000 Microchip Technology Inc.
; Initialize PORTG data
; Set RG<1:0> as inputs
;
;
; Select Bank 5
; Configure PORTG as
; digital
;
;
; Value used to init
;
the data direction
RG<7:2> as outputs
latches before
register
data direction
ST
Input
Buffer
I/O pin