PIC17LC756A-08I/L Microchip Technology, PIC17LC756A-08I/L Datasheet - Page 142

• Manufacturer Part Number: PIC17LC756A-08I/L
• Description: IC MCU OTP 16KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC17C7XX
15.1.7
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
TABLE 15-1:
DS30289B-page 142
07h, Unbanked INTSTA
10h, Bank 4
11h, Bank 4
14h, Bank 6
11h, Bank 6
13h, Bank 6
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
Address
SLEEP OPERATION
SSPCON1 WCOL SSPOV SSPEN
PIR2
PIE2
SSPBUF
SSPSTAT
REGISTERS ASSOCIATED WITH SPI OPERATION
Name
SSPIE
Synchronous Serial Port Receive Buffer/Transmit Register
SSPIF
PEIF
Bit 7
SMP
T0CKIF
BCLIF
BCLIE
Bit 6
CKE
ADIF
ADIE
Bit 5
T0IF
D/A
INTF
Bit 4
CKP
—
—
P
SSPM3 SSPM2 SSPM1
CA4IE
CA4IF
PEIE
Bit 3
S
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP inter-
rupt flag bit will be set and if enabled, will wake the
device from SLEEP.
15.1.8
A RESET disables the MSSP module and terminates
the current transfer.
T0CKIE
CA3IE
CA3IF
Bit 2
R/W
EFFECTS OF A RESET
TX2IF
TX2IE
Bit 1
T0IE
UA
SSPM0 0000 0000 0000 0000
RC2IF
RC2IE
INTE
Bit 0
BF
2000 Microchip Technology Inc.
0000 0000 0000 0000
000- 0010 000- 0010
000- 0000 000- 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
POR, BOR
MCLR, WDT