PIC17LC756A-08I/L Microchip Technology, PIC17LC756A-08I/L Datasheet - Page 64

• Manufacturer Part Number: PIC17LC756A-08I/L
• Description: IC MCU OTP 16KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC17C7XX
8.3
The table read allows the program memory to be read.
This allows constants to be stored in the program mem-
ory space and retrieved into data memory when
needed. Example 8-2 reads the 16-bit value at program
memory address TBLPTR. After the dummy byte has
been read from the TABLATH, the TABLATH is loaded
with the 16-bit data from program memory address
TBLPTR and then increments the TBLPTR value. The
first read loads the data into the latch and can be con-
sidered a dummy read (unknown data loaded into ’f’).
INDF0 should be configured for either auto-increment
or auto-decrement.
FIGURE 8-7:
FIGURE 8-8:
DS30289B-page 64
AD15:AD0
Instruction
Instruction
Executed
Fetched
Table Reads
ALE
WR
OE
AD15:AD0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
’1’
Instruction
Instruction
Executed
INST (PC-1)
Fetched
TABLRD1
PC
TABLRD TIMING
TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)
ALE
WR
OE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
’1’
TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1 TABLRD2 cycle2
INST (PC-1)
TABLRD
TABLRD2
PC
PC+1
TABLRD cycle1
Data read cycle
INST (PC+1)
PC+1
TBL1 Data in 1
EXAMPLE 8-2:
MOVLW
MOVWF
MOVLW
MOVWF
TABLRD
TLRD
TABLRD
INST (PC+2)
Data read cycle
TABLRD cycle2
PC+2
TBL
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
0, 1, DUMMY
1, INDF0
0, 1, INDF0
Data in
Data read cycle
TABLE READ
TBL2
INST (PC+2)
INST (PC+1)
2000 Microchip Technology Inc.
PC+2
; Dummy read,
;
;
; Read HI byte
;
; Read LO byte
;
;
;
Data in 2
;
;
;
Updates TABLATH
Increments TBLPTR
of TABLATH
of TABLATL and
Update TABLATH
Increment TBLPTR
INST (PC+3)
address
INST (PC+2)
PC+3