P87C52X2FN,112 NXP Semiconductors, P87C52X2FN,112 Datasheet - Page 52

• Manufacturer Part Number: P87C52X2FN,112
• Description: IC 80C51 MCU 256 RAM 40DIP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C52X2FN,112

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 33 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 935269602112; P87C52X2FN; P87C52X2FN

1. Not tested.
*
**
Philips Semiconductors
PROGRAMMING AND VERIFICATION CHARACTERISTICS
T
NOTE:
NOTES:
2003 Jan 24
amb
SYMBOL
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
V
I
1/t
t
t
t
t
t
t
t
t
t
t
t
t
FOR PROGRAMMING CONFIGURATION SEE FIGURE 40.
FOR VERIFICATION CONDITIONS SEE FIGURE 42.
SEE TABLE 9.
PP
AVGL
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
AVQV
ELQZ
EHQZ
GHGL
PP
= 21 C to +27 C, V
CLCL
P0.0 – P0.7
ALE/PROG
(A0 – A12)
P1.0–P1.7
P2.0–P2.5
(D0 – D7)
PORT 0
EA/V
P2.7
P3.4
PP
**
Programming supply voltage
Programming supply current
Oscillator frequency
Address setup to PROG low
Address hold after PROG
Data setup to PROG low
Data hold after PROG
P2.7 (ENABLE) high to V
V
V
PROG width
Address to data valid
ENABLE low to data valid
Data float after ENABLE
PROG high to PROG low
PP
PP
setup to PROG low
hold after PROG
CC
t
t
AVGL
DVGL
t
= 5 V 10%, V
EHSH
t
SHGL
t
GLGH
PP
SS
PROGRAMMING
= 0 V (See Figure 43)
ADDRESS
DATA IN
PARAMETER
Figure 43. Programming and Verification
*
t
GHGL
LOGIC 0
t
t
GHDX
GHAX
52
t
GHSL
LOGIC 1
t
ELQV
VERIFICATION
t
AVQV
ADDRESS
48t
48t
48t
48t
48t
LOGIC 1
DATA OUT
P80C3xX2; P80C5xX2;
MIN
12.5
10
10
90
10
CLCL
CLCL
CLCL
CLCL
CLCL
4
0
*
48t
48t
48t
t
EHQZ
MAX
13.0
50
110
CLCL
CLCL
CLCL
6
1
P87C5xX2
Product data
SU01414
UNIT
MHz
mA
V
s
s
s
s