P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 35

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
13.5.4
A command bit initiates an action within the transfer layer of the CAN-controller. The Command Register appears to the
CPU as a read/write memory, except for the bits CMR.0 (TR) to CMR.3 (COS), which return a HIGH if being read.
Table 33 Command Register (address 1)
Table 34 Description of the CMR bits
1996 Jun 27
BIT SYMBOL
7
6
5
4
3
2
1
0
8-bit microcontroller with on-chip CAN
RX0A
RX0A
RX1A
WUM
SLP
COS
RRB
AT
TR
7
C
OMMAND
RX0 Active. See Table 35; note 1.
RX1 Active. See Table 35; note 1.
Wake-up Mode (note 2). If the value of WUM is:
Sleep (note 3). If the value of SLP is:
Clear Overrun Status (note 4). If the value of COS is:
Release Receive Buffer (note 5). If the value of RRB is:
Abort Transmission (note 6). If the value of AT is:
Transmission Request (note 7). If the value of TR is:
RX1A
R
HIGH (single ended), then the difference of the RX signals to the internal reference voltage
is used for wake up.
LOW (differential), then the differential signal between RX0 and RX1 is used for wake up.
HIGH (sleep), then the CAN-controller enters sleep mode if no CAN interrupt is pending and there
is no bus activity.
LOW (wake up), then the CAN-controller functions normally.
HIGH (clear), then the Data Overrun status bit is set to LOW (see Table 37).
LOW (no action), then there is no action.
HIGH (released), then the Receive Buffer attached to the CPU is released.
LOW (no action), then there is no action.
HIGH (present) and if not already in progress, a pending Transmission Request is cancelled.
LOW (absent), then there is no action.
HIGH (present), then a message shall be transmitted.
LOW (absent), then there is no action.
EGISTER
6
(CMR)
WUM
5
SLP
4
35
FUNCTION
COS
3
RRB
2
AT
1
Product specification
P8xC592
1
TR
0
2
AV
DD