ST7FLITEU05M6TR STMicroelectronics, ST7FLITEU05M6TR Datasheet - Page 41

• Manufacturer Part Number: ST7FLITEU05M6TR
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU05M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ST7LITEU05 ST7LITEU09
7.5
7.5.1
7.5.2
Register description
Multiplexed IO reset control register 1 (MUXCR1)
Reset value: 0000 0000 (00h)
Multiplexed IO reset control register 0 (MUXCR0)
Reset value: 0000 0000 (00h)
Bits 15:0 = MIR[15:0]
Table 9.
Address
MIR15
(Hex.)
0047h
0048h
MIR7
7
7
This 16-bit register is read/write by software but can be written only once between two
reset events. It is cleared by hardware after a reset; When both MUXCR0 and
MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To
configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.
These registers are one-time writable only.
To configure PA3 as general purpose output:
After power-on / reset, the application program has to configure the I/O port by writing
to these registers as described above. Once the pin is configured as an I/O output, it
cannot be changed back to a reset pin by the application code.
To configure PA3 as RESET:
An internally generated reset (such as POR, WDG, illegal opcode) will clear the two
registers and the pin will act again as a reset function. Otherwise, a power-down is
required to put the pin back in reset configuration.
Reset Value
Reset Value
MIR14
MIR6
Multiplexed IO register map and reset values
MUXCR0
MUXCR1
Register
Label
MIR13
MIR5
MIR15
MIR7
7
0
0
MIR12
MIR4
MIR14
MIR6
Read/write once only
Read/write once only
6
0
0
MIR13
MIR5
MIR11
MIR3
5
0
0
MIR12
MIR4
Supply, reset and clock management
4
0
0
MIR10
MIR2
MIR11
MIR3
3
0
0
MIR10
MIR2
2
0
0
MIR9
MIR1
MIR1
MIR9
1
0
0
MIR8
MIR0
0
0
MIR0
MIR8
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0
0
0