ST7FLITEU05M6TR STMicroelectronics, ST7FLITEU05M6TR Datasheet - Page 58

• Manufacturer Part Number: ST7FLITEU05M6TR
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU05M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Power saving modes
9.5.1
58/139
Figure 31. AWUFH mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
Register description
AWUFH control/status register (AWUCSR)
Reset value: 0000 0000 (00h)
Bits 7:3 = Reserved
interrupt). Refer to Table 10, “Interrupt mapping,” on page 44 for more details.
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
0
7
0
0
(AWUCSR.AWUEN=1)
HALT INSTRUCTION
N
(Active-Halt disabled)
WATCHDOG
WDGHALT
RESET
1
INTERRUPT
Y
1)
0
Read/Write
ENABLE
3)
256 OR 512 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
I[1:0] BITS
AWU RC OSC
I[1:0] BITS
N
CYCLE
0
RESET
WATCHDOG
Y
DELAY
DISABLE
2)
XX
XX
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
AWUF
4)
4)
ST7LITEU05 ST7LITEU09
AWUM
AWUEN
0