ST7FLITES5Y0M6TR STMicroelectronics, ST7FLITES5Y0M6TR Datasheet - Page 56

• Manufacturer Part Number: ST7FLITES5Y0M6TR
• Description: IC MCU 8BIT 1K FLASH 16-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITES5Y0M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Processor Series: ST7FLITESx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7LITE0xY0, ST7LITESxY0
12-BIT AUTORELOAD TIMER (Cont’d)
11.2.6 Register Description
TIMER CONTROL STATUS REGISTER (ATC-
SR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:5 = Reserved, must be kept cleared.
Bit 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR register. It indicates the
transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Caution:
When set, the OVF bit stays high for 1 f
cycle, (up to 1ms depending on the clock selec-
tion).
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and clear by
56/124
1
7
0
f
LTIMER
Counter Clock Selection
0
(1 ms timebase @ 8 MHz)
Reserved
0
OFF
f
CPU
CK1
CK0
OVF
CK1
OVFIE CMPIE
0
0
1
1
COUNTER
CK0
0
1
0
1
0
hardware after a reset. It allows to mask the inter-
rupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
COUNTER REGISTER HIGH (CNTRH)
Read only
Reset Value: 0000 0000 (00h)
COUNTER REGISTER LOW (CNTRL)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter is incre-
mented continuously as soon as a counter clock is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. The CNTRH register can be in-
cremented between the two reads, and in order to
be accurate when f
should take this into account when CNTRL and
CNTRH are read. If CNTRL is close to its highest
value, CNTRH could be incremented before it is
read.
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR register.
CN7
15
0
7
CN6
0
CN5
0
CN4
0
TIMER
CN11
CN3
=f
CPU
CN10
CN2
, the software
CN9
CN1
CN8
CN0
8
0