Z8F0412SJ020SG Zilog, Z8F0412SJ020SG Datasheet - Page 133

• Manufacturer Part Number: Z8F0412SJ020SG
• Description: IC ENCORE MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0412SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: Z8F041xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4107; Z8F0412SJ020SG

PS022517-0508
SPI Baud Rate Generator
necessary for SS to deassert between characters to generate the interrupt. The SPI in
SLAVE mode also generates an interrupt if the SS signal deasserts prior to transfer of all
the bits in a character (see description of Slave Abort Error). Writing a 1 to the IRQ bit in
the SPI Status Register clears the pending SPI interrupt request. The
cleared to 0 by the ISR to generate future interrupts. To start the transfer process, an SPI
interrupt can be forced by software writing a 1 to the STR bit in the SPICTL Register.
If the SPI is disabled, an SPI interrupt can be generated by a BRG time-out. This timer
function must be enabled by setting the BIRQ bit in the SPICTL Register. This BRG
time-out does not set the IRQ bit in the SPISTAT Register, just the SPI interrupt bit in the
interrupt controller.
In SPI MASTER mode, the BRG creates a lower frequency serial clock (SCK) for data
transmission synchronization between the Master and the external Slave. The input to the
BRG is the system clock. The SPI Baud Rate High and Low Byte Registers combine to
form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The SPI baud
rate is calculated using the following equation:
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 X 65536 = 131072).
When the SPI is disabled, BRG functions as a basic 16-bit timer with interrupt on
time-out. Follow the steps below to configure BRG as a timer with interrupt on time-out:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control Register to 0.
2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte
3. Enable BRG timer function and associated interrupt by setting the BIRQ bit in the SPI
When configured as a general-purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ]
registers.
Control Register to 1.
SPI Baud Rate (bits/s)
=
System Clock Frequency (Hz)
------------------------------------------------------------------------------ -
2xBRG[15:0]
Z8 Encore! XP
Product Specification
Serial Peripheral Interface
IRQ
®
bit must be
F0822 Series
120