Z8F0412SJ020SG Zilog, Z8F0412SJ020SG Datasheet - Page 99

• Manufacturer Part Number: Z8F0412SJ020SG
• Description: IC ENCORE MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0412SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: Z8F041xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4107; Z8F0412SJ020SG

Table 48. Watchdog Timer Control Register (WDTCTL)
Watchdog Timer Control Register Definitions
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
Reset or Stop Mode Recovery Event
Power-On Reset
Reset through RESET pin assertion
Reset through WDT time-out
Reset through the OCD (OCTCTL[1] set to 1)
Reset from STOP Mode through the DBG Pin driven Low
Stop Mode Recovery through GPIO pin transition
Stop Mode Recovery through WDT time-out
Watchdog Timer Control Register
POR
7
All three Watchdog Timer Reload Registers must be written in this order. There must be
no other register writes between each of these operations. If a register write occurs, the
lock state machine resets and no further writes occur unless the sequence is restarted. The
value in the Watchdog Timer Reload Registers is loaded into the counter when the WDT is
first enabled and every time a WDT instruction is executed.
The Watchdog Timer Control Register (WDTCTL), detailed in
Register that indicates the source of the most recent Reset event, a Stop Mode Recovery
event, and a WDT time-out. Reading this register resets the upper four bits to 0.
Writing the
(WDTCTL) address unlocks the three Watchdog Timer Reload Byte registers (WDTU,
WDTH, and WDTL) to allow changes to the time-out period. These write operations to
the WDTCTL address produce no effect on the bits in the WDTCTL. The locking
mechanism prevents spurious writes to the Reload registers.
POR—Power-On Reset Indicator
If this bit is set to 1, a POR event occurred. This bit is reset to 0, if a WDT time-out or
Stop Mode Recovery occurs. This bit is also reset to 0, when the register is read.
See descriptions below
STOP
6
55H
,
AAH
WDT
unlock sequence to the Watchdog Timer Control Register
5
EXT
4
FF0H
R
POR STOP WDT
3
1
0
0
1
1
0
0
Z8 Encore! XP
0
0
0
0
0
1
1
2
0
Reserved
Table
Product Specification
0
0
1
0
0
0
1
48, is a Read-Only
EXT
1
®
0
1
0
0
0
0
0
F0822 Series
Watchdog Timer
0
86