ST62T10CM6 STMicroelectronics, ST62T10CM6 Datasheet - Page 51

• Manufacturer Part Number: ST62T10CM6
• Description: IC MCU 8BIT OTP 2K 20 SOIC
• Manufacturer: STMicroelectronics
• Series: ST6r

Specifications of ST62T10CM6

• Core Processor: ST6
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Cpu Family: ST6
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 64Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOP
• Processor Series: ST62T1x
• Core: ST6
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
• Minimum Operating Temperature: - 40 C
• Controller Family/series: ST6
• No. Of I/o's: 12
• Ram Memory Size: 64Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 497-2097-5

8-BIT TIMER (Cont’d)
8.2.7 Register Description
PRESCALER COUNTER REGISTER (PSCR)
Address: 0D2h - Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = PSCR7: Not used, always read as “0”.
Bits 6:0 = PSCR[6:0] Prescaler LSB.
TIMER COUNTER REGISTER (TCR)
Address: 0D3h - Read / Write
Reset Value: 1111 1111 (FFh)
Bits 7:0 = TCR[7:0] Timer counter bits.
TIMER STATUS CONTROL REGISTER (TSCR)
Address: 0D4h - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = TMZ Timer Zero bit.
A low-to-high transition indicates that the timer
count register has underflowed. It means that the
TCR value has changed from 00h to FFh.
This bit must be cleared by user software.
0: Counter has not underflowed
1: Counter underflow occurred
Bit 6 = ETI Enable Timer Interrupt.
When set, enables the timer interrupt request. If
Table 15. 8-Bit Timer Register Map and Reset Values
PSCR
TCR7
TMZ
Address
(Hex.)
7
7
7
7
0D2h
0D3h
0D4h
PSCR
TCR6
ETI
6
PSCR
Reset Value
TCR
Reset Value
TSCR
Reset Value
PSCR
TOUT DOUT
TCR5
Register Label
5
PSCR
TCR4
4
PSCR
TCR3
PSI
3
PSCR
TCR2
PSCR7
PS2
TCR7
TMZ
2
7
0
1
0
PSCR
TCR1
PS1
1
PSCR6
TCR6
ETI
6
1
1
0
PSCR
TCR0
PS0
0
0
0
0
PSCR5
TOUT
TCR5
5
1
1
0
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
0: Interrupt disabled (reset state)
1: Interrupt enabled
Bit 5 = TOUT Timer Output Control.
When low, this bit selects the input mode for the
TIMER pin. When high the output mode is select-
ed.
0: Input mode (reset state)
1: Output mode, the TIMER pin is configured as
push-pull output
Bit 4 = DOUT Data Output.
Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only).
Bit 3 = PSI: Prescaler Initialize bit.
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSE=“1” both counter and prescaler are not run-
ning
0: Counting disabled
1: Counting enabled
Bits 1:0 = PS[2:0] Prescaler Mux. Select.
These bits select the division ratio of the prescaler
register.
Table 14. Prescaler Division Factors
ST6208C/ST6209C/ST6210C/ST6220C
PS2
PSCR4
DOUT
0
0
0
0
1
1
1
1
TCR4
4
1
1
0
PSCR3
TCR3
PSI
3
1
1
0
PS1
1
0
0
1
1
0
0
1
PSCR2
TCR2
PS2
2
1
1
0
PS0
1
0
1
0
1
0
1
0
PSCR1
TCR1
PS1
1
1
1
0
Divided by
128
PSCR0
16
32
64
TCR0
8
1
2
4
PS0
51/104
0
1
1
0
1