ST7FLITE39F2M6TR STMicroelectronics, ST7FLITE39F2M6TR Datasheet - Page 110

• Manufacturer Part Number: ST7FLITE39F2M6TR
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
If LHE bit is set due to this error during Fields other
than LIN Synch Field or if LASE bit is reset then
the current received Header is discarded and the
SCI searches for a new Break Field.
Note on LIN Header Time-out Limit
According to the LIN specification, the maximum
length of a LIN Header which does not cause a
timeout
T
T
When checking this timeout, the slave node is de-
synchronized for the reception of the LIN Break
and Synch fields. Consequently, a margin must be
allowed, taking into account the worst case: This
occurs when the LIN identifier lasts exactly 10
T
and Synch fields last 49 - 10 = 39T
riods.
Assuming the slave measures these first 39 bits
with a desynchronized clock of 15.5%. This leads
to a maximum allowed Header Length of:
39 x (1/0.845) T
= 56.15 T
A margin is provided so that the time-out occurs
when the header length is greater than 57
T
T
Figure 61. LIN Synch Field Measurement
110/173
BIT_MASTER
BIT_MASTER
BIT_MASTER
BIT_SLAVE
BIT_SLAVE
SM = Synch Measurement Register (15 bits)
T
T
CPU
BR
LIN Synch Break
= Baud Rate period
= CPU period
BIT_SLAVE
is
periods. If it is less than or equal to 57
periods, then no timeout occurs.
.
refers to the master baud rate.
periods. In this case, the LIN Break
BIT_MASTER
equal
Extra
LPR(n)
‘1’
to
+ 10T
T
Start
Bit
BR
1.4 * (34 + 1) = 49
T
LPR = T
BR
BIT_MASTER
BIT_MASTER
= 16.LP.T
Bit0
BR
Measurement = 8.T
/ (16.T
Bit1 Bit2
CPU
pe-
CPU
LIN Synch Field
) = Rounding (SM / 128)
LIN Header Length
Even if no timeout occurs on the LIN Header, it is
possible to have access to the effective LIN head-
er Length (T
This allows monitoring at software level the
T
This feature is only available when LHDM bit = 1
or when LASE bit = 1.
Mute Mode and Errors
In mute mode when LHDM bit = 1, if an LHE error
occurs during the analysis of the LIN Synch Field
or if a LIN Header Time-out occurs then the LHE
bit is set but it does not wake up from mute mode.
In this case, the current header analysis is discard-
ed. If needed, the software has to reset LSF bit.
Then the SCI searches for a new LIN header.
In mute mode, if a framing error occurs on a data
(which is not a break), it is discarded and the FE bit
is not set.
When LHDM bit = 1, any LIN header which re-
spects the following conditions causes a wake-up
from mute mode:
- A valid LIN Break Field (at least 11 dominant bits
followed by a recessive bit)
- A valid LIN Synch Field (without deviation error)
- A LIN Identifier Field without framing error. Note
that a LIN parity error on the LIN Identifier Field
does not prevent wake-up from mute mode.
- No LIN Header Time-out should occur during
Header reception.
Bit3
FRAME_MAX
BR
Bit4
= SM.T
Bit5
CPU
condition given by the LIN protocol.
HEADER
Bit6
) through the LHL register.
Bit7
Stop
Bit
LPR(n+1)
Next
Start
Bit