ST7FLITE39F2M6TR STMicroelectronics, ST7FLITE39F2M6TR Datasheet - Page 67

• Manufacturer Part Number: ST7FLITE39F2M6TR
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
11.2.6 Register Description
TIMER CONTROL STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = Reserved.
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Bit 5 = ICIE IC Interrupt Enable.
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
Bit 2 = OVF1 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the TCSR register. It indicates the tran-
sition of the counter1 CNTR1 from FFh to ATR1
value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 1 = OVFIE1 Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
7
0
f
LTIMER
Counter Clock Selection
ICF
6
(1 ms timebase @ 8 MHz)
ICIE
OFF
OFF
f
CPU
CK1
CK0
OVF1 OVFIE1 CMPIE
CK1
0
1
0
1
CK0
0
1
1
0
0
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when any of the CMPFx bit is
set.
0: Output compare interrupt disabled.
1: Output Compare interrupt enabled.
COUNTER REGISTER 1 HIGH (CNTR1H)
Read only
Reset Value: 0000 0000 (000h)
COUNTER REGISTER 1 LOW (CNTR1L)
Read only
Reset Value: 0000 0000 (000h)
Bits 15:12 = Reserved.
Bits 11:0 = CNTR1[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter CNTR1 is
incremented continuously as soon as a counter
clock is selected. To obtain the 12-bit value, soft-
ware should read the counter value in two consec-
utive read operations. The CNTR1H register can
be incremented between the two reads, and in or-
der to be accurate when f
should take this into account when CNTR1L and
CNTR1H are read. If CNTR1L is close to its high-
est value, CNTR1H could be incremented before it
is read.
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR1 regis-
ter.
CNTR1_
15
0
7
7
CNTR1_
0
6
CNTR1_
0
5
CNTR1_
0
4
TIMER
CNTR1_
CNTR1_
11
3
=f
CNTR1_
CNTR1_
CPU
10
ST7LITE3xF2
2
, the software
CNTR1_
CNTR1_
9
1
67/173
CNTR1_
CNTR1_
8
8
0
0
1