IC MCU 8BIT W/ADC 16-SOIC

ST62T62CM3

Manufacturer Part NumberST62T62CM3
DescriptionIC MCU 8BIT W/ADC 16-SOIC
ManufacturerSTMicroelectronics
SeriesST6
ST62T62CM3 datasheet
 


Specifications of ST62T62CM3

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o9Program Memory Size1.8KB (1.8K x 8)
Program Memory TypeOTPEeprom Size64 x 8
Ram Size128 x 8Voltage - Supply (vcc/vdd)3 V ~ 6 V
Data ConvertersA/D 4x8bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case16-SOIC (0.300", 7.5mm Width)
Processor SeriesST62T6xCoreST6
Data Bus Width8 bitData Ram Size128 B
Interface TypeSPI, UARTMaximum Clock Frequency8 MHz
Number Of Programmable I/os9Number Of Timers2
Maximum Operating Temperature+ 125 CMounting StyleSMD/SMT
Development Tools By SupplierST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-IIMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 4 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Connectivity-  
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Features
3.0 to 6.0 V supply operating range
8 MHz maximum clock frequency
-40 to +125°C operating temperature range
Run, Wait and Stop Modes
5 Interrupt vectors
Look-up table capability in Program Memory
Data storage in Program Memory:
User selectable size
Data RAM: 128 bytes
Data EEPROM: 64 bytes (not in ST6252C devices)
User programmable options
9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
5 I/O lines can sink up to 30 mA to drive LEDs or
TRIACs directly
8-bit Timer / Counter with 7-bit programmable
prescaler
8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
Digital watchdog
Oscillator Safe Guard (not in ST6262B devices)
Low Voltage Detector for safe Reset (not in
ST6262B devices)
8-bit A/D converter with 4 analog inputs
On-chip Clock oscillator can be driven by quartz
crystal ceramic resonator or RC network
User configurable Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 emulation and development
system (connects to an MS-DOS PC via a
parallel port)
March 2009
8-bit MCUs with A/D converter,
safe reset, auto-reload timer and EEPROM
(See end of Datasheet for Ordering Information)
Table 1. Device summary
DEVICE
ST6252C
ST6262C
ST6262B
Rev. 4
ST6252C ST6262B
ST6262C
PDIP16
PSO16
SSOP16
CDIP16W
Program memory
(Bytes)
1836
1836
1836
EEPROM
(Bytes)
-
64
64
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ST62T62CM3 Summary of contents

  • Page 1

    Features 3.0 to 6.0 V supply operating range ■ 8 MHz maximum clock frequency ■ -40 to +125°C operating temperature range ■ Run, Wait and Stop Modes ■ 5 Interrupt vectors ■ Look-up table capability in Program Memory ■ Data ...

  • Page 2

    ST6252C ST6262B ST6262C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6252C and ST6262C devices are low cost members of the ST62xx 8-bit HCMOS family of mi- crocontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building ...

  • Page 4

    ST6252C ST6262B ST6262C 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins ...

  • Page 5

    MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3. Memory Addressing Diagram PROGRAM SPACE 0000h ...

  • Page 6

    ... U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with a protection set can therefore not be ac- cepted. ...

  • Page 7

    MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and ...

  • Page 8

    ST6252C ST6262B ST6262C MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program ...

  • Page 9

    MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM (DRBR) Address: E8h — Write only 7 DRBR - - - - 4 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit ...

  • Page 10

    ST6252C ST6262B ST6262C MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged ...

  • Page 11

    MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, ...

  • Page 12

    ... TEST/V programming flow of the ST62T62C is described in the User Manual of the EPROM Programming Board. The MCUs can be programmed with the ST62E6xB EPROM programming tools available from STMicroelectronics. Table 5. ST62T52C/T62C Program Memory Map Device Address 0000h-087Fh 0880h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h ...

  • Page 13

    ... FFh. Partial or total programming of EEP- ROM data memory can be performed either through the application software or through an ex- ST6252C ST6262B ST6262C ternal programmer. Any STMicroelectronics tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data mem- ory. ...

  • Page 14

    ST6252C ST6262B ST6262C 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory ...

  • Page 15

    CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ad- dress of ...

  • Page 16

    ST6252C ST6262B ST6262C 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a ...

  • Page 17

    CLOCK SYSTEM (Cont’d) Turning on the main oscillator is achieved by re- setting the OSCOFF bit of the A/D Converter Con- trol Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up ...

  • Page 18

    ST6252C ST6262B ST6262C CLOCK SYSTEM (Cont’d) Figure 9. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency ...

  • Page 19

    CLOCK SYSTEM (Cont’d) Figure 11. Clock Circuit Block Diagram MAIN OSCILLATOR Figure 12. Maximum Operating Frequency (f Maximum FREQUENCY (MHz 2.5 Notes this area, operation is guaranteed at the quartz ...

  • Page 20

    ST6252C ST6262B ST6262C 3.2 RESETS The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD) ...

  • Page 21

    RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. ...

  • Page 22

    ST6252C ST6262B ST6262C RESETS (Cont’d) 3.2.6 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (locat program ROM starting at address 0FFEh). A jump to ...

  • Page 23

    RESETS (Cont’d) Table 6. Register Reset Status Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Mode Control Register AR TIMER Status/Control 1 Register AR TIMER Status/Control 2Register ...

  • Page 24

    ST6252C ST6262B ST6262C 3.4 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can ...

  • Page 25

    DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.4.1 Digital Watchdog Register This register is set to 0FEh on Reset: bit ...

  • Page 26

    ST6252C ST6262B ST6262C DIGITAL WATCHDOG (Cont’d) 3.4.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110 Bit Watchdog Control bit If the hardware option is selected, this ...

  • Page 27

    DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions ...

  • Page 28

    ST6252C ST6262B ST6262C 3.5 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction ...

  • Page 29

    INTERRUPTS (Cont’d) 3.5.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context ...

  • Page 30

    ST6252C ST6262B ST6262C INTERRUPTS (Cont’d) 3.5.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and ...

  • Page 31

    INTERRUPTS (Cont’d) Figure 21. Interrupt Block Diagram FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B Bits PORT C PBE Bits SPIDIV Register SPINT bit SPIE bit SPIMOD Register AR TIMER TIMER1 V DD ...

  • Page 32

    ST6252C ST6262B ST6262C 3.6 POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described ...

  • Page 33

    POWER SAVING MODE (Cont’d) 3.6.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart sequence ...

  • Page 34

    ST6252C ST6262B ST6262C 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt ...

  • Page 35

    I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). Table ...

  • Page 36

    ST6252C ST6262B ST6262C I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe ...

  • Page 37

    I/O PORTS (Cont’d) Table 12. I/O Port Option Selections MODE AVAILABLE ON Input PA4-PA5 Reset state( PB0, PB6-PB7 PC2-PC3 Reset state if PULL-UP PB2-PB3, option disabled PA4-PA5 Input PB0,,PB6-PB7 Reset state PC2-PC3 Reset state if PULL-UP option enabled PB2-PB3 Input ...

  • Page 38

    ST6252C ST6262B ST6262C I/O PORTS (Cont’d) 4.1.3 ARTimer alternate functions When bit PWMOE of register ARMC is low, pin ARTIMout/PB7 is configured as any standard pin of port B through the port registers. When PW- MOE is high, ARTMout/PB7 is ...

  • Page 39

    TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 Figure 25. shows the Timer Block Diagram. The content of the 8-bit counter can ...

  • Page 40

    ST6252C ST6262B ST6262C TIMER (Cont’d) 4.2.1 Timer Operation The Timer prescaler is clocked by the prescaler clock input (f ÷ 12). INT The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR ...

  • Page 41

    TIMER (Cont’d) A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i. write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit ...

  • Page 42

    ST6252C ST6262B ST6262C 4.3 AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected ...

  • Page 43

    AUTO-RELOAD TIMER (Cont’d) Figure 27. AR Timer Block Diagram f INT INT U AR PRESCALER X PS0-PS2 CC0-CC1 PB6/ ARTIMin SL0-SL1 EF SYNCHRO DATA BUS 8 AR COMPARE REGISTER 8 COMPARE 8 8-Bit 7-Bit AR COUNTER 8 ...

  • Page 44

    ST6252C ST6262B ST6262C AUTO-RELOAD TIMER (Cont’d) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI- Mout, the contents of ...

  • Page 45

    AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation. In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit capture operation from ...

  • Page 46

    ST6252C ST6262B ST6262C AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: D5h — Read/Write Reset status: 00h 7 TCLD TEN PWMOE EIE CPIE The AR Mode Control Register ARMC is used to program the different ...

  • Page 47

    AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: D7h — Read/Write 7 PS2 PS1 PS0 D4 SL1 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler itself is not ...

  • Page 48

    ST6252C ST6262B ST6262C 4.4 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- ...

  • Page 49

    A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ply ...

  • Page 50

    ST6252C ST6262B ST6262C 5 SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. ...

  • Page 51

    INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, ...

  • Page 52

    ST6252C ST6262B ST6262C INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either ...

  • Page 53

    INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or ...

  • Page 54

    ST6252C ST6262B ST6262C Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 ...

  • Page 55

    Opcode Map Summary (Continued) LOW 8 9 1000 1001 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 2 JRNZ ...

  • Page 56

    ST6252C ST6262B ST6262C 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage ...

  • Page 57

    RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A Operating Supply Voltage (Except ST626xB ROM devices Operating Supply Voltage (ST626xB ROM devices) 2) Oscillator Frequency (Except ST626xB ROM devices) f OSC 2) Oscillator Frequency (ST626xB ROM devices) ...

  • Page 58

    ST6252C ST6262B ST6262C 6.3 DC ELECTRICAL CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V ...

  • Page 59

    DC ELECTRICAL CHARACTERISTICS (Cont’ -40 to +85°C unless otherwise specified)) A Symbol Parameter V LVD Threshold in power- LVD threshold in powerdown dn Low Level Output Voltage All Output pins V OL Low Level Output Voltage ...

  • Page 60

    ST6252C ST6262B ST6262C 6.5 A/D CONVERTER CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter Res Resolution (1) (2) A Total Accuracy TOT t Conversion Time C ZIR Zero Input Reading FSR Full Scale Reading Analog Input ...

  • Page 61

    Figure 31. Vol versus Iol on all I/O port at Vdd= This curves represents typical variations and is given for guidance only Figure 32. Vol versus Iol on all I/O port at T=25°C ...

  • Page 62

    ST6252C ST6262B ST6262C Figure 34. Vol versus Iol for High sink (30mA) I/O ports at Vdd= This curves represents typical variations and is given for guidance only Figure 35. Voh versus Ioh ...

  • Page 63

    Figure 37. Idd WAIT versus V 2.5 2 1 This curves represents typical variations and is given for guidance only Figure 38. Idd STOP versus This curves represents ...

  • Page 64

    ST6252C ST6262B ST6262C Figure 40. Idd WAIT versus V 2.5 2 1 This curves represents typical variations and is given for guidance only Figure 41. Idd RUN versus This ...

  • Page 65

    Figure 43. RC frequency versus This curves represents typical variations and is given for guidance only Figure 44. RC frequency versus 0.1 3 This curves represents typical variations and is given for guidance only ...

  • Page 66

    ST6252C ST6262B ST6262C 7 PACKAGE MECHANICAL DATA In order to meet environmental requirements, ST offers these devices in different grades of ECO- ® PACK packages, depending on their level of en- vironmental compliance. ECOPACK Figure 45. 16-Pin Plastic Dual In-Line ...

  • Page 67

    PACKAGE MECHANICAL DATA (Cont’d) Figure 47. 16-Pin Plastic Small Outline Package, 300-mil Width Figure 48. 16-Pin Plastic Shrink Small Outline Package 45× ...

  • Page 68

    ST6252C ST6262B ST6262C THERMAL CHARACTERISTICS Symbol Parameter RthJA Thermal Resistance 68/75 Test Conditions Min. PDIP16 PSO16 Value Unit Typ. Max. 55 °C/W 75 ...

  • Page 69

    ... ORDERING INFORMATION 8.1 OTP/EPROM versions Table 22. OTP/EPROM version ordering information Sales Type Memory (Bytes) ST62E62CF1 1836 EPROM ST62T52CM6 ST62T52CM3 ST62T62CM6 ST62T62CM3 ST62T52CB6 ST62T52CB3 ST62T62CB6 ST62T62CB3 ST62T52CN6 ST62T52CN3 ST62T62CN6 ST62T62CN3 8.1.1 IMPORTANT NOTE For OTP devices, data retention and programmability must be guaranteed by a screening procedure. Re- fer to Application Note AN886 ...

  • Page 70

    ... MCU. The listing is then returned to 70/75 the customer who must thoroughly check, com- plete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agree- ment for the production of the specific customer MCU. ...

  • Page 71

    ROM versions Table 25. ROM version ordering information Sales Type ROM ST6252CB1/XXX ST6252CB6/XXX ST6252CB3/XXX ST6252CM1/XXX ST6252CM6/XXX 1836 Bytes ST6252CM3/XXX ST6252CN1/XXX ST6252CN6/XXX ST6252CN3/XXX ST6262BB1/XXX ST6262BB6/XXX ST6262BB3/XXX ST6262BM1/XXX ST6262BM6/XXX 1836 Bytes ST6262BM3/XXX ST6262BN1/XXX ST6262BN6/XXX ST6262BN3/XXX The ST6252C and ST6262B are mask ...

  • Page 72

    ... MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agreement for the creation of the specific customer mask. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points ...

  • Page 73

    ... Software Activation [ ] Hardware Activation [ ] Enabled [ ] Disabled [ ] Enabled [ ] Disabled [ ] Enabled [ ] Disabled [ ] Enabled Fuse is blown by STMicroelectronics [ ] Fuse can be blown by the customer [ ] Disabled [ ] Enabled [ ] Disabled [ ] Enabled [ ] Disabled [ ] Enabled [ ] Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 74

    ST6252C ST6262B ST6262C 9 REVISION HISTORY Table 27. Document revision history Date Rev. Modification of “Additional Notes for EEPROM Parallel Mode” (p.13) Changed f In section 4.2 on page 41: vector #4 instead of vector #3 for the timer interrupt ...

  • Page 75

    ... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...