Z8F1622VS020SG Zilog, Z8F1622VS020SG Datasheet - Page 110

• Manufacturer Part Number: Z8F1622VS020SG
• Description: IC ENCORE MCU FLASH 16K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F1622VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F162x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4243; Z8F1622VS020SG

Table 48. Watchdog Timer Control Register (WDTCTL)
Watchdog Timer Control Register Definitions
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
Watchdog Timer Control Register
POR
7
2. Write
3. Write the Watchdog Timer Reload Upper Byte register (WDTU).
4. Write the Watchdog Timer Reload High Byte register (WDTH).
5. Write the Watchdog Timer Reload Low Byte register (WDTL).
All steps of the Watchdog Timer Reload Unlock sequence must be written in the order just
listed. There must be no other register writes between each of these operations. If a regis-
ter write occurs, the lock state machine resets and no further writes can occur, unless the
sequence is restarted. The value in the Watchdog Timer Reload registers is loaded into the
counter when the Watchdog Timer is first enabled and every time a WDT instruction is
executed.
The Watchdog Timer Control (WDTCTL) register
indicates the source of the most recent Reset event, indicates a Stop Mode Recovery event,
and indicates a Watchdog Timer time-out. Reading this register resets the upper four bits
to 0.
Writing the
ter address unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH, and
WDTL) to allow changes to the time-out period. These write operations to the WDTCTL
register address produce no effect on the bits in the WDTCTL register. The locking mech-
anism prevents spurious writes to the Reload registers.
See descriptions below
STOP
AAH
6
55H
to the Watchdog Timer Control register (WDTCTL).
,
AAH
WDT
unlock sequence to the Watchdog Timer Control (WDTCTL) regis-
5
EXT
4
FF0H
R
3
(Table
Z8 Encore! XP
Reserved
48) is a Read-Only register that
2
0
Product Specification
1
®
F64XX Series
Watchdog Timer
SM
0
96