Z8F1622VS020SG Zilog, Z8F1622VS020SG Datasheet - Page 86

• Manufacturer Part Number: Z8F1622VS020SG
• Description: IC ENCORE MCU FLASH 16K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F1622VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F162x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4243; Z8F1622VS020SG

Table 31. IRQ1 Enable High Bit Register (IRQ1ENH)
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
IRQ2 Enable High and Low Bit Registers
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
R/W
R/W
7
0
7
0
PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit.
For selection of either Port A or Port D as the interrupt source, see
Register
PADxENL—Port A or Port D Bit[x] Interrupt Request Enable Low Bit
For selection of either Port A or Port D as the interrupt source, see
Register
The IRQ2 Enable High and Low Bit registers (see
a priority encoded enabling for interrupts in the Interrupt Request 2 register. Priority is
generated by setting bits in each register.
Table 33. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x]
0
0
1
on page 74.
on page 74.
R/W
R/W
6
0
6
0
0
1
0
R/W
R/W
5
0
5
0
Disabled
Priority
R/W
R/W
Level 1
Level 2
4
0
4
0
FC4H
FC5H
Table 33
R/W
R/W
3
0
3
0
Description
Disabled
Nominal
Table 34
describes the priority control for IRQ2.
Low
Z8 Encore! XP
R/W
R/W
and
2
0
2
0
Table 35
Product Specification
Interrupt Port Select
Interrupt Port Select
R/W
R/W
1
0
1
0
®
on page 73) form
Interrupt Controller
F64XX Series
R/W
R/W
0
0
0
0
72