Z8F1622VS020SG Zilog, Z8F1622VS020SG Datasheet - Page 162

• Manufacturer Part Number: Z8F1622VS020SG
• Description: IC ENCORE MCU FLASH 16K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F1622VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F162x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4243; Z8F1622VS020SG

PS019921-0308
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 7-
bit addressing.
Follow the steps below for a transmit operation on a 10-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE interrupt by writing the first slave address byte to the
5. Software asserts the START bit of the I
6. The I
7. The I
8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is
9. Software responds by writing the second byte of address into the contents of the I
10. The I
11. If the I
12. The I
13. The I
14. Software responds by writing a data byte to the I
15. The I
I
register.
asserted.
Data register.
signal.
during the next high period of SCL, the I
Status register. Continue with
If the slave does not acknowledge the first address byte, the I
NCKI bit and clears the ACK bit in the I
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I
NCKI bits. The transaction is complete (ignore the following steps).
register.
bit has been sent, the Transmit interrupt is asserted.
signal.
2
C Data register. The least-significant bit must be 0 for the write operation.
2
2
2
2
2
2
2
C interrupt asserts because the I
C Controller sends the START condition to the I
C Controller loads the I
C Controller shifts the rest of the first byte of address and write bit out the SDA
C Controller loads the I
C Controller shifts the second address byte out the SDA signal. After the first
C Controller completes shifting the contents of the shift register on the SDA
2
C slave acknowledges the first address byte by pulling the SDA signal low
2
C Controller sends the STOP condition on the bus and clears the STOP and
2
2
step
C Shift register with the contents of the I
C Shift register with the contents of the I
12.
2
2
C Control register.
C Control register to enable Transmit interrupts.
2
C Data register is empty.
2
C Control register.
2
2
C Status register. Software responds to the
C Controller sets the ACK bit in the I
11110XX
2
C Data register.
Z8 Encore! XP
2
C slave.
. The two bits
Product Specification
2
C Controller sets the
®
F64XX Series
XX
2
2
C Data
C Data
I2C Controller
are the two
2
C
2
C
148