ST7FMC1K2T6/TR STMicroelectronics, ST7FMC1K2T6/TR Datasheet - Page 61

• Manufacturer Part Number: ST7FMC1K2T6/TR
• Description: IC MCU 8BIT 8K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC1K2T6/TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FMC1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

WINDOW WATCHDOG (Cont’d)
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This operation
must occur only when the counter value is lower
than the window register value. The value to be
stored in the WDGCR register must be between
FFh and C0h (see
– Enabling the watchdog:
– Controlling the downcounter:
When Software Watchdog is selected (by option
byte), the watchdog is disabled after a reset. It is
enabled by setting the WDGA bit in the WDGCR
register, then it cannot be disabled again except
by a reset.
When Hardware Watchdog is selected (by option
byte), the watchdog is always active and the
WDGA bit is not used.
This downcounter is free-running: It counts down
even if the watchdog is disabled. When the
watchdog is enabled, the T6 bit must be set to
prevent generating an immediate reset.
The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see
proximate Timeout
Figure
Duration). The timing varies
35):
Figure 35. Ap-
Note: The T6 bit can be used to generate a soft-
ware reset (the WDGA bit is set and the T6 bit is
cleared).
– Watchdog Reset on Halt option
10.1.4 Using Halt Mode with the WDG
If Halt mode with Watchdog is enabled by option
byte (no watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see
The window register (WDGWR) contains the
high limit of the window: To prevent a reset, the
downcounter must be reloaded when its value is
lower than the window register value and greater
than 3Fh.
dog process.
If the watchdog is activated and the watchdog re-
set on halt option is selected, then the HALT in-
struction will generate a Reset.
Figure 37
describes the window watch-
ST7MC1xx/ST7MC2xx
Figure
36).
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