ST72F361J9T6 STMicroelectronics, ST72F361J9T6 Datasheet - Page 41

• Manufacturer Part Number: ST72F361J9T6
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

POWER SAVING MODES (Cont’d)
Figure 27. ACTIVE HALT Timing Overview
Figure 28. ACTIVE HALT Mode Flow-chart
(Active Halt enabled)
(AWUCSR.AWUEN=0)
INSTRUCTION
HALT INSTRUCTION
RUN
N
(MCCSR.OIE=1)
HALT
INTERRUPT
ACTIVE
HALT
Y
DELAY (AFTER RESET)
256 OR 4096 CYCLE
INTERRUPT
3)
RESET
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
CYCLE DELAY
RESET
Y
VECTOR
2)
FETCH
XX
XX
OFF
OFF
OFF
RUN
ON
ON
ON
ON
ON
ON
10
4)
4)
Notes:
1. This delay occurs only if the MCU exits ACTIVE
2. Peripheral clocked with an external clock
3. Only the RTC interrupt and some specific inter-
4. Before servicing an interrupt, the CC register is
HALT mode by means of a RESET.
source can still be active.
rupts can exit the MCU from ACTIVE HALT
mode (such as external interrupt). Refer to
Table 9, “Interrupt Mapping,” on page 33
more details.
pushed on the stack. The I[1:0] bits in the CC
register are set to the current software priority
level of the interrupt routine and restored when
the CC register is popped.
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