ST72F361J7T3 STMicroelectronics, ST72F361J7T3 Datasheet - Page 199

• Manufacturer Part Number: ST72F361J7T3
• Description: IC MCU 8BIT 48K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J7T3

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 112. RESET Pin Protection When LVD Is Enabled
Figure 113. RESET Pin Protection When LVD Is Disabled
Note 1:
1.1 The reset network protects the device against parasitic resets.
1.2 The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
1.3 Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
1.4 Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
Note 2:
2.1 When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is recommend-
ed to filter noise on the reset line.
2.2. In case a capacitive power supply is used, it is recommended to connect a1MW pull-down resistor to the RESET pin
to discharge any residual voltage induced by this capacitive power supply (this will add 5µA to the power consumption of
the MCU).
2.3. Tips when using the LVD:
EXTERNAL
Required
– 1. Check that all recommendations related to reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709. If this
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up margin-
EXTERNAL
CIRCUIT
cannot be done, it is recommended to put a 100nF + 1MW pull-down on the RESET pin.
ality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: Replace 10nF pull-down on
the RESET pin with a 5µF to 20µF capacitor.
RESET
RESET
IL
USER
max. level specified in
INJ(RESET)
Recommended
0.01μF
in
Section 12.2.2 on page
0.01μF
Section
1MΩ
Optional
(note 2.2)
V
12.10.1. Otherwise the reset will not be taken into account internally.
DD
4.7kΩ
179.
V
V
DD
DD
R
R
ON
ON
Filter
Filter
1)2)
1)
GENERATOR
GENERATOR
PULSE
PULSE
INTERNAL
RESET
INTERNAL
RESET
WATCHDOG
LVD RESET
WATCHDOG
ST72361
ST72XXX
ST72XXX
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