ST72F321AR6T6 STMicroelectronics, ST72F321AR6T6 Datasheet - Page 165

• Manufacturer Part Number: ST72F321AR6T6
• Description: MCU 8BIT 32KB FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321AR6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4842

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
12.11.2 I
Subject to general operating conditions for V
f
Figure 95. Typical Application with I
Notes:
1. Data based on standard I
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV
5. At 4MHz f
t
CPU
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
t
su(SDA)
t
t
su(STA)
su(STO)
t
t
h(SDA)
h(STA)
r(SDA)
r(SCL)
f(SDA)
SDA
SCK
f(SCL)
I
C
, and T
2
t
C BUS
f(SDA)
b
2
C - Inter IC Control Interface
CPU
t
A
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
h(STA)
unless otherwise specified.
, max.I
START
4.7kΩ
t
w(SCKH)
t
r(SDA)
2
C speed (400kHz) is not achievable. In this case, max. I
V
2
DD
C protocol requirement, not tested in production.
t
w(SCKL)
Parameter
4.7kΩ
V
DD
t
su(SDA)
2
t
r(SCK)
C Bus and Timing Diagram
100Ω
100Ω
t
h(SDA)
t
DD
f(SCK)
DD
,
SDAI
SCLI
and 0.7xV
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SDAI and SCLI). The ST7 I
requirements of the Standard I
protocol described in the following table.
ST72XXX
Standard mode I
Min
250
0
4.7
4.7
4.0
4.7
4.0
4.0
DD
ST72321Rx ST72321ARx ST72321Jx
3)
.
1)
4)
2
Max
1000
C speed will be approximately 260KHz.
300
400
2
1)
C
t
su(STA)
20+0.1C
20+0.1C
t
su(STO)
Min
Fast mode I
100
0
1.3
0.6
0.6
0.6
0.6
1.3
2
2)
C interface meets the
1)
t
w(STO:STA)
STOP
2
b
b
C communication
REPEATED START
Max
900
300
300
400
2
C
5)
3)
1)
START
165/193
Unit
pF
μs
ns
μs
μs
μs