ST10R172LT1 STMicroelectronics, ST10R172LT1 Datasheet - Page 16

• Manufacturer Part Number: ST10R172LT1
• Description: MCU 16BIT ROMLESS LV 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R172LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition

ST10R172L - INTERRUPT AND TRAP FUNCTIONS
5.2
Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware
traps cause immediate non-maskable system reaction similar to a standard interrupt service
(branching to a dedicated vector table location). The occurrence of a hardware trap is
additionally signified by an individual bit in the trap flag register (TFR). Except when another
higher prioritized trap service is in progress, a hardware trap will interrupt any actual program
execution. In turn, hardware trap services can not normally be interrupted by standard or PEC
interrupts. The following table shows all of the possible exceptions or error conditions that can
arise during run-time:
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1
Exception Condition
Reset Functions:
Class A Hardware Traps:
Class B Hardware Traps:
Reserved
Software Traps
Hardware Reset
Software Reset
Watchdog Timer Overflow
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Undefined opcode
Protected instruction fault
Illegal word operand access ILLOPA
Illegal instruction access
Illegal external bus access
TRAP Instruction
Hardware traps
Table 3 Exceptions or error conditions
Trap Flag
NMI
STKOF
STKUF
UNDOPC
PRTFLT
ILLINA
ILLBUS
Trap Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
Vector
Location
00’0000
00’0000
00’0000
00’0008
00’0010
00’0018
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
[2C
Any [00’0000
– 00’01FC
steps of 4
h
– 3C
h
h
h
h
h
h
h
h
h
]
]
h
Trap
Number
00
00
00
02
04
06
0A
0A
0A
0A
0A
[0B
Any
[00
h
h
h
h
h
h
h
h
h
h
h
h
h
– 7F
– 0F
h
h
]
]
Trap
Priority
III
III
III
II
II
II
I
I
I
I
I
Current
CPU
Priority