ST10R172LT1 STMicroelectronics, ST10R172LT1 Datasheet - Page 64

• Manufacturer Part Number: ST10R172LT1
• Description: MCU 16BIT ROMLESS LV 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R172LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition

ST10R172L - ELECTRICAL CHARACTERISTICS
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1
(Demux Bus)
RSTOUT
RD, WR
The ST10R172L is reset in its default state asynchronously with RSTIN. The internal
RAM content may be altered if an internal write access is in progress.
On power-up, RSTIN must be asserted t
Internal pullup devices are active on the PORT0 lines, so - input level is high if the respec-
tive pin is left open - or is low if the respective pin is connected to an external pulldown
device.
The ST10R172L starts execution here at address 00’0000h.
RSTOUT stays active until execution of the EINIT (end of initialization) instruction.
Activation of the IO pins is controlled by software
PORT0
Other IOs
Internal
RSTIN
Signal
PORT1
Reset
Figure 24 External asynchronous hardware reset (power-up reset): Vpp low
ALE
5)
6)
1)
t
77
3)
t
792)
79
after a stabilized CPU clock signal is available.
t
74
t
t
73
75
t
76
t
78
4)