ST72F264G2B6 STMicroelectronics, ST72F264G2B6 Datasheet - Page 139

• Manufacturer Part Number: ST72F264G2B6
• Description: MCU 8-BIT 8K FLASH 32-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F264G2B6

• Mfg Application Notes: ST7 Checksum Capability, AN1070 App Note
• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Processor Series: ST72F2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• For Use With: 497-6423 - BOARD EVAL BASED ON ST72264G1497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5570

CLOCK CHARACTERISTICS (Cont’d)
13.5.5 PLL Characteristics
Note:
1. Data characterized but not tested.
Figure 74. PLL Jitter vs. Signal frequency
Note 1: Measurement conditions: f
V
f
∆ f
OSC
DD(PLL)
Symbol
CPU
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
/f
CPU
2000
PLL Operating Range
PLL input frequency range
Instantaneous PLL jitter
Application Signal Frequency (KHz)
1000
Parameter
500
250
CPU
1)
PLL ON
PLL OFF
= 4MHz, T
125
T
T
f
f
OSC
OSC
A
A
1
0 to 70
-40 to +85
= 4 MHz.
= 2 MHz.
A
Conditions
= 25°C
°C
°C
The user must take the PLL jitter into account in
the application (for example in serial communica-
tion or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore the longer the
period of the application signal, the less it will be
impacted by the PLL jitter.
Figure 74
cation signals in the range 125kHz to 2MHz. At fre-
quencies of less than 125KHz, the jitter is negligi-
ble.
ST72260Gx, ST72262Gx, ST72264Gx
shows the PLL jitter integrated on appli-
Min
3.5
4.5
2
Typ
1.0
2.5
Max
5.5
5.5
2.5
4.0
4
139/172
MHz
Unit
%
%
V