ST10R272LT1 STMicroelectronics, ST10R272LT1 Datasheet - Page 21

• Manufacturer Part Number: ST10R272LT1
• Description: MCU 16BIT ROMLESS LV 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R272LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R2x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 16 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

of repetition that remains to complete the sequence. If the Repeat Unit is used in the interrupt
routine, MRW must be saved by the user and restored before the end of the interrupt routine.
Note
MAC interrupt
The MAC can generate an interrupt according to the value of the status flags C (carry), SV
(overflow), E (extension) or SL (limit) of the MSW. The MAC interrupt is globally enabled when
the MIE flag in MCW is set. When it is enabled the flags C, SV, E or SL can triggered a MAC
interrupt when they are set provided that the corresponding mask flag CM, VM, EM or LM in
MCW is also set. A MAC interrupt request set the MIR flag in MSW, this flag must be reset by
the user during the interrupt routine otherwise the interrupt processing restarts when
returning from the interrupt routine.
The MAC interrupt is implemented as a Class B hardware trap (trap number Ah - trap priority
I). The associated Trap Flag in the TFR register is MACTRP, bit #6 of the TFR (Remember
that this flag must also be reset by the user in the case of an MAC interrupt request).
As the MAC status flags are updated (or eventually written by software) during the Execute
stage of the pipeline, the response time of a MAC interrupt request is 3 instruction cycles (see
Figure 3). It is the number of instruction cycles required between the time the request is sent
and the time the first instruction located at the interrupt vector location enters the pipeline.
Note that the IP value stacked after a MAC interrupt does not point to the instruction that
triggers the interrupt.
FETCH
DECODE
EXECUTE
WRITEBACK
The Repeat Count should be used with caution. In this case MR should be written as
0. In general MR should not be set by the user otherwise correct instruction
processing can not be guaranteed.
Figure 7 Pipeline diagram for MAC interrupt response time
N
N-1
N-2
N-3
N+1
N
N-1
N-2
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
N+2
N+1
N
N-1
MAC Interrupt Request
N+3
N+2
N+1
N
Response Time
N+4
TRAP (1)
N+2
N+1
I1
TRAP (2)
TRAP (1)
N+2
I2
I1
TRAP (2)
TRAP (1)
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