ST10R272LT1 STMicroelectronics, ST10R272LT1 Datasheet - Page 60

• Manufacturer Part Number: ST10R272LT1
• Description: MCU 16BIT ROMLESS LV 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R272LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R2x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 16 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ST10R272L - ELECTRICAL CHARACTERISTICS
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1
Parameter
Data hold after WR
ALE rising edge after RD,
WR
Address hold after RD, WR
Address hold after WRH
Latched CS setup to ALE
Unlatched CS setup to ALE
Latched CS low to Valid
Data In
Unlatched CS low to Valid
Data In
Latched CS hold after RD,
WR
Unlatched CS hold after RD,
WR
Address setup to RdCs,
WrCs (with RW-delay)
Address setup to RdCs,
WrCs (no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
24
26
28
28h
38
38u
39
39u
41
41u
82
83
46
47
48
49
50
Table 18 Demultiplexed bus
CC
CC
CC
CC
CC
CC
SR
SR
CC
CC
CC
CC
SR
SR
CC
CC
CC
Max CPU Clock 50MHz
min.
5 +
-5 +
0
-9+
-1
-8
-7 +
3 +
–
–
3 +
0
-7
13 +
3 +
–
–
11 +
21 +
13 +
(no t
(no t
+
+
(no t
t
t
t
t
t
t
2t
F (
F (
F (
F
A
F
t
t
2t
t
t
t
F
A
F)
F)
C
C
C
A
t
t
t
F)
F>0)
F>0)
F>0)
A
max.
–
–
–
–
3 +
–
13
+
23
+
–
–
–
–
3 +
13 +
–
–
–
t
t
C
C
t
t
A
C
+ 2
+ 2
t
C
t
t
A
A
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
TCL - 5 +
-5 +
0 (no
-9 +
-1 (no
-8 +
-7 +
TCL - 7 +
–
–
TCL - 7 +
0 (no
-7 +
2TCL - 7 +
TCL - 7 +
–
–
2TCL - 9 +
3TCL - 9 +
2TCL - 7 +
t
t
t
t
t
F
F (
F (
A
F (
t
t
F
F
t
F
t
t
t
)
)
F>0)
F>0)
F>0)
)
t
t
t
2t
F
A
F
2t
t
t
t
C
C
C
A
A
max.
–
–
–
–
3 +
–
3TCL - 17
+
4TCL - 17
+
–
–
–
–
2TCL - 17 +
3TCL - 17 +
–
–
–
t
t
C
C
t
A
+ 2
+ 2
t
t
A
A
t
t
C
C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns