ST7FMC2M9T6 STMicroelectronics, ST7FMC2M9T6 Datasheet - Page 74

• Manufacturer Part Number: ST7FMC2M9T6
• Description: MCU 8BIT 60K FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2M9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Processor Series: ST7FMC2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 5
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4867

ST7MC1xx/ST7MC2xx
ON-CHIP PERIPHERALS (Cont’d)
INPUT CAPTURE
CONTROL / STATUS REGISTER (ARTICCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved, always read as 0.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
determine the trigger event polarity on the corre-
sponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel inter-
rupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by
software reading the corresponding ARTICRx reg-
ister. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x.
1: An input capture has occurred on channel x.
74/309
1
7
0
0
CS2
CS1
CIE2
CIE1
CF2
CF1
0
INPUT CAPTURE REGISTERS (ARTICRx)
Read only
Reset Value: 0000 0000 (00h)
Bit 7:0 = IC[7:0] Input Capture Data
These read only bits are set and cleared by hard-
ware. An ARTICRx register contains the 8-bit
auto-reload counter value transferred by the input
capture channel x event.
IC7
7
IC6
IC5
IC4
IC3
IC2
IC1
IC0
0